From 5da6eed52e9eeb94001f98d18469e1692125ce9f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 12 Apr 2021 10:54:57 +0000 Subject: [PATCH] rename JTAG port in adder test experiments10_verilog (success compile) --- experiments10/coriolis2/ioring.py | 8 ++++---- experiments10_verilog/add.py | 8 ++++---- experiments10_verilog/coriolis2/settings.py | 2 +- experiments10_verilog/doDesign.py | 10 +++++----- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/experiments10/coriolis2/ioring.py b/experiments10/coriolis2/ioring.py index 3842e0e..33522ca 100644 --- a/experiments10/coriolis2/ioring.py +++ b/experiments10/coriolis2/ioring.py @@ -23,10 +23,10 @@ chip = { 'pads.ioPadGauge' : 'pxlib', [ 'p_f2' , 'f(2)', 'f(2)' ], # , 'f_oe' ], [ 'p_f3' , 'f(3)', 'f(3)' ], # , 'f_oe' ], # JTAG - [ 'p_tck_0' , 'tck', 'tck'], # 2nd clock - [ 'p_tms_0' , 'tms', 'tms'], - [ 'p_tdo_0' , 'tdo', 'tdo'], - [ 'p_tdi_0' , 'tdi', 'tdi'], + [ 'p_jtag_tck' , 'jtag_tck', 'jtag_tck'], # 2nd clock + [ 'p_jtag_tms' , 'jtag_tms', 'jtag_tms'], + [ 'p_jtag_tdo' , 'jtag_tdo', 'jtag_tdo'], + [ 'p_jtag_tdi' , 'jtag_tdi', 'jtag_tdi'], ], 'pads.south' : [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ], diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py index 33311d3..bcf0965 100644 --- a/experiments10_verilog/add.py +++ b/experiments10_verilog/add.py @@ -20,10 +20,10 @@ class ADD(Elaboratable): # set up JTAG self.jtag = TAP(ir_width=4) - self.jtag.bus.tck.name = 'tck' - self.jtag.bus.tms.name = 'tms' - self.jtag.bus.tdo.name = 'tdo' - self.jtag.bus.tdi.name = 'tdi' + self.jtag.bus.tck.name = 'jtag_tck' + self.jtag.bus.tms.name = 'jtag_tms' + self.jtag.bus.tdo.name = 'jtag_tdo' + self.jtag.bus.tdi.name = 'jtag_tdi' # have to create at least one shift register self.sr = self.jtag.add_shiftreg(ircode=4, length=3) diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py index 7c24dff..5c739c2 100644 --- a/experiments10_verilog/coriolis2/settings.py +++ b/experiments10_verilog/coriolis2/settings.py @@ -35,7 +35,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) af = CRL.AllianceFramework.get() env = af.getEnvironment() - env.setCLOCK( '^clk|^ck|^tck' ) + env.setCLOCK( '^clk|^ck|^jtag_tck' ) env.setPOWER( 'vdd' ) env.setGROUND( 'vss' ) env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py index addccdb..dad7f43 100644 --- a/experiments10_verilog/doDesign.py +++ b/experiments10_verilog/doDesign.py @@ -42,12 +42,12 @@ def scriptMain ( **kw ): , (IoPin.SOUTH, None, 'power_0' , 'vdd' ) , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' ) , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' ) - , (IoPin.EAST , None, 'p_tms_0' , 'tms' , 'tms' ) - , (IoPin.EAST , None, 'p_tdo_0' , 'tdo' , 'tdo' ) + , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms' , 'jtag_tms' ) + , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo' , 'jtag_tdo' ) , (IoPin.EAST , None, 'ground_0' , 'vss' ) , (IoPin.EAST , None, 'clk' , 'clk' , 'clk' ) - , (IoPin.EAST , None, 'p_tck' , 'tck' , 'tck' ) - , (IoPin.EAST , None, 'p_tdi_0' , 'tdi' , 'tdi' ) + , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck' , 'jtag_tck' ) + , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi' , 'jtag_tdi' ) , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) , (IoPin.NORTH, None, 'ioground_0' , 'iovss' ) , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' ) @@ -85,7 +85,7 @@ def scriptMain ( **kw ): rvalue = chipBuilder.doPnR() chipBuilder.save() - CRL.Gds.save(ls180Conf.chip) + CRL.Gds.save(adderConf.chip) except Exception, e: helpers.io.catch( e ) -- 2.30.2