From 5daf1a2296e6070445e7e22bd5def8d012d6d58d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 10 Oct 2019 21:52:09 +0200 Subject: [PATCH] cpu: cleanup/re-align --- litex/soc/cores/cpu/lm32/core.py | 4 ++-- litex/soc/cores/cpu/minerva/core.py | 4 ++-- litex/soc/cores/cpu/picorv32/core.py | 4 ++-- litex/soc/cores/cpu/rocket/core.py | 20 ++++++++++---------- litex/soc/cores/cpu/vexriscv/core.py | 10 +++++----- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 47d65fa0..f41345bb 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -34,8 +34,8 @@ class LM32(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 8bc86829..e52731e5 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -29,8 +29,8 @@ class Minerva(CPU): def __init__(self, platform, variant="standard"): assert variant is "standard", "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = wishbone.Interface() self.dbus = wishbone.Interface() diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index a190cb77..0d934c87 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -55,8 +55,8 @@ class PicoRV32(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant + self.platform = platform + self.variant = variant self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 2c2025ab..6ec2cc5e 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -79,22 +79,22 @@ class RocketRV64(CPU): def __init__(self, platform, variant="standard"): assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant - self.platform = platform - self.variant = variant + self.platform = platform + self.variant = variant self.reset = Signal() self.interrupt = Signal(4) - self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4) - self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4) + self.mem_axi = mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4) + self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4) - self.mem_wb64 = mem_wb64 = wishbone.Interface(data_width=64, adr_width=29) + self.mem_wb64 = mem_wb64 = wishbone.Interface(data_width=64, adr_width=29) self.mmio_wb64 = mmio_wb64 = wishbone.Interface(data_width=64, adr_width=29) - self.mem_wb32 = mem_wb32 = wishbone.Interface() + self.mem_wb32 = mem_wb32 = wishbone.Interface() self.mmio_wb32 = mmio_wb32 = wishbone.Interface() - self.buses = [mem_wb32, mmio_wb32] + self.buses = [mem_wb32, mmio_wb32] # # # @@ -210,16 +210,16 @@ class RocketRV64(CPU): ) # adapt axi interfaces to wishbone - mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb64, base_address=0)) + mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb64, base_address=0)) mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb64, base_address=0)) # NOTE: AXI2Wishbone FSMs must be reset with the CPU! self.comb += [ - mem_a2w.reset.eq(ResetSignal() | self.reset), + mem_a2w.reset.eq( ResetSignal() | self.reset), mmio_a2w.reset.eq(ResetSignal() | self.reset), ] # down-convert wishbone from 64 to 32 bit data width - mem_dc = wishbone.Converter(mem_wb64, mem_wb32) + mem_dc = wishbone.Converter(mem_wb64, mem_wb32) mmio_dc = wishbone.Converter(mmio_wb64, mmio_wb32) self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 2accda02..c281943e 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -102,11 +102,11 @@ class VexRiscv(CPU, AutoCSR): self.platform = platform self.variant = variant self.external_variant = None - self.reset = Signal() - self.ibus = ibus = wishbone.Interface() - self.dbus = dbus = wishbone.Interface() - self.buses = [ibus, dbus] - self.interrupt = Signal(32) + self.reset = Signal() + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() + self.buses = [ibus, dbus] + self.interrupt = Signal(32) self.cpu_params = dict( i_clk=ClockSignal(), -- 2.30.2