From 5db59a02ace208db29be203b2f404d4505ecdc19 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sat, 24 Apr 2021 13:29:09 +0200 Subject: [PATCH] Correct settings for experiment10_verilog & FreePDK45. --- experiments10_verilog/freepdk_c4m45/Makefile | 1 + .../freepdk_c4m45/coriolis2/settings.py | 4 +- .../freepdk_c4m45/doDesign.py | 60 +++++++++---------- .../freepdk_c4m45/netlists.txt | 11 ++-- 4 files changed, 41 insertions(+), 35 deletions(-) diff --git a/experiments10_verilog/freepdk_c4m45/Makefile b/experiments10_verilog/freepdk_c4m45/Makefile index 72c1116..e86078c 100755 --- a/experiments10_verilog/freepdk_c4m45/Makefile +++ b/experiments10_verilog/freepdk_c4m45/Makefile @@ -1,4 +1,5 @@ + PDKMASTER_TOP = $(shell pwd)/../../../c4m-pdk-freepdk45 LOGICAL_SYNTHESIS = Yosys PHYSICAL_SYNTHESIS = Coriolis DESIGN_KIT = FreePDK_C4M45 diff --git a/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py b/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py index cc10a52..c0ddc5c 100644 --- a/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py +++ b/experiments10_verilog/freepdk_c4m45/coriolis2/settings.py @@ -18,7 +18,7 @@ if not NdaDirectory: helpers.setNdaTopDir( NdaDirectory ) import Cfg -from CRL import AllianceFramework +from CRL import AllianceFramework, RoutingLayerGauge from helpers import overlay, l, u, n from NDA.node45.freepdk45_c4m import techno, FlexLib, LibreSOCIO @@ -38,7 +38,9 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg: cfg.misc.verboseLevel2 = True cfg.etesian.graphics = 3 cfg.etesian.spaceMargin = 0.10 + cfg.anabatic.topRoutingLayer = 'metal6' cfg.katana.eventsLimit = 4000000 af = AllianceFramework.get() + af.getRoutingGauge('FlexLib').getLayerGauge( 5 ).setType( RoutingLayerGauge.PowerSupply ) env = af.getEnvironment() env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py index 613e7e3..125040e 100644 --- a/experiments10_verilog/freepdk_c4m45/doDesign.py +++ b/experiments10_verilog/freepdk_c4m45/doDesign.py @@ -3,6 +3,7 @@ from __future__ import print_function import sys import traceback import CRL +from CRL import RoutingLayerGauge import helpers from helpers.io import ErrorMessage from helpers.io import WarningMessage @@ -32,9 +33,9 @@ def scriptMain ( **kw ): global af rvalue = True coreSize = u(3.5*90.0) - chipBorder = u(4.5*214.0 + 10*13.0) + chipBorder = u(4.5*214.0 + 10*4.0) try: - helpers.setTraceLevel( 550 ) + #helpers.setTraceLevel( 550 ) cell, editor = plugins.kwParseMain( **kw ) cell = af.getCell( 'add', CRL.Catalog.State.Logical ) if cell is None: @@ -44,30 +45,30 @@ def scriptMain ( **kw ): # Spec: # | Side | Pos | Instance | Pad net |Core net | Direction | ioPadsSpec = [ - (IoPin.SOUTH, None, 'p_a0' , 'a(0)' , 'a(0)' ) - , (IoPin.SOUTH, None, 'p_a1' , 'a(1)' , 'a(1)' ) - , (IoPin.SOUTH, None, 'iopower_0' , 'iovdd' ) - , (IoPin.SOUTH, None, 'power_0' , 'vdd' ) - , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' ) - , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' ) - , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms' , 'jtag_tms' ) - , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo' , 'jtag_tdo' ) - , (IoPin.EAST , None, 'ground_0' , 'vss' ) - , (IoPin.EAST , None, 'p_sys_clk' , 'sys_clk' , 'sys_clk' ) - , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck' , 'jtag_tck' ) - , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi' , 'jtag_tdi' ) - , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) - , (IoPin.NORTH, None, 'ioground_0' , 'iovss' ) - , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' ) - , (IoPin.NORTH, None, 'ground_1' , 'vss' ) - , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' ) - , (IoPin.NORTH, None, 'p_sys_rst' , 'sys_rst' , 'sys_rst' ) - , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' ) - , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' ) - , (IoPin.WEST , None, 'power_1' , 'vdd' ) - , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' ) - , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' ) - , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' ) + (IoPin.SOUTH, None, 'p_a0' , 'a(0)' , 'a(0)' ) + , (IoPin.SOUTH, None, 'p_a1' , 'a(1)' , 'a(1)' ) + , (IoPin.SOUTH, None, 'iopower_0' , 'iovdd' ) + , (IoPin.SOUTH, None, 'power_0' , 'vdd' ) + , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' ) + , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' ) + , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms', 'jtag_tms') + , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo', 'jtag_tdo') + , (IoPin.EAST , None, 'ground_0' , 'vss' ) + , (IoPin.EAST , None, 'p_sys_clk' , 'sys_clk' , 'sys_clk' ) + , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck', 'jtag_tck') + , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi', 'jtag_tdi') + , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' ) + , (IoPin.NORTH, None, 'ioground_0' , 'iovss' ) + , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' ) + , (IoPin.NORTH, None, 'ground_1' , 'vss' ) + , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' ) + , (IoPin.NORTH, None, 'p_sys_rst' , 'sys_rst' , 'sys_rst' ) + , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' ) + , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' ) + , (IoPin.WEST , None, 'power_1' , 'vdd' ) + , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' ) + , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' ) + , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' ) ] adderConf = ChipConf( cell, ioPads=ioPadsSpec ) adderConf.cfg.etesian.bloat = 'nsxlib' @@ -77,11 +78,10 @@ def scriptMain ( **kw ): adderConf.cfg.anabatic.searchHalo = 2 adderConf.cfg.anabatic.globalIterations = 20 adderConf.cfg.anabatic.routingGauge = 'FlexLib' - adderConf.cfg.anabatic.topRoutingLayer = 'METAL10' - adderConf.cfg.block.spareSide = u(7*13) + adderConf.cfg.block.spareSide = u(7*4) #adderConf.cfg.chip.padCoreSide = 'North' - adderConf.cfg.chip.supplyRailWidth = u(35) - adderConf.cfg.chip.supplyRailPitch = u(90) + adderConf.cfg.chip.supplyRailWidth = u(15) + adderConf.cfg.chip.supplyRailPitch = u(45) adderConf.editor = editor adderConf.useSpares = True adderConf.useClockTree = True diff --git a/experiments10_verilog/freepdk_c4m45/netlists.txt b/experiments10_verilog/freepdk_c4m45/netlists.txt index 599bb5a..de4cb12 100644 --- a/experiments10_verilog/freepdk_c4m45/netlists.txt +++ b/experiments10_verilog/freepdk_c4m45/netlists.txt @@ -1,5 +1,8 @@ add -fsm -idblock -irblock -jtag +cmpt_add +cmpt_fsm +cmpt_idblock +cmpt_irblock +cmpt_sram0 +cmpt_sram1 +cmpt_jtag -- 2.30.2