From 5ddb6dcedd517272c0bbb9391a9a3cb0ca9d9bed Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 24 Dec 2018 19:11:07 +0000 Subject: [PATCH] back.rtlil: unbreak d47c1f8a. --- nmigen/back/rtlil.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index bc98975..c51b4b9 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -644,7 +644,7 @@ def convert_fragment(builder, fragment, name, top): memories[memory] = module.memory(width=memory.width, size=memory.depth, name=memory.name) addr_bits = bits_for(memory.depth) - data_parts = ["{}'".format(memory.width * memory.depth)] + data_parts = [] for addr in range(memory.depth): if addr < len(memory.init): data = memory.init[addr] @@ -653,7 +653,8 @@ def convert_fragment(builder, fragment, name, top): data_parts.append("{:0{}b}".format(data, memory.width)) module.cell("$meminit", ports={ "\\ADDR": rhs_compiler(ast.Const(0, addr_bits)), - "\\DATA": "".join(data_parts), + "\\DATA": "{}'".format(memory.width * memory.depth) + + "".join(reversed(data_parts)), }, params={ "MEMID": memories[memory], "ABITS": addr_bits, -- 2.30.2