From 5dff543fcedd2c5e2bc4458737be79f5fab49b5b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 9 May 2021 15:41:33 +0100 Subject: [PATCH] code-comments about ls180 imports --- libresoc/core.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libresoc/core.py b/libresoc/core.py index 5e6c02a..681ccf6 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -301,7 +301,10 @@ class LibreSoC(CPU): # XXX normally this is NOT done, however to avoid import problems # in litex, move the import into where it is optionally called # then, for non-ls180 platforms, huge numbers of dependencies - # behind these simple-looking imports are not needed + # behind these simple-looking imports are not needed. + # For normal FPGA usage ("standard" variants) you DO NOT need this. + # it is ONLY for ASICs, for managing JTAG TAP Boundary Scans. + from soc.config.pinouts import get_pinspecs from soc.debug.jtag import Pins from libresoc.ls180 import io -- 2.30.2