From 5e176a613ef2eda92aa65736763a562dc42a50fe Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 15 Aug 2019 08:32:07 +0000 Subject: [PATCH] [AArch64] Add more unpredicated MOVPRFX alternatives FABD and some immediate instructions were missing MOVPRFX alternatives. This is tested by the ACLE patches but is really an independent improvement. 2019-08-15 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (add3, sub3) (3, *add3, *mul3) (*fabd3): Add more MOVPRFX alternatives. Co-Authored-By: Kugan Vivekanandarajah From-SVN: r274513 --- gcc/ChangeLog | 7 +++ gcc/config/aarch64/aarch64-sve.md | 71 +++++++++++++++++++------------ 2 files changed, 51 insertions(+), 27 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7a68a4554e2..6bfbd9976df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-08-15 Richard Sandiford + Kugan Vivekanandarajah + + * config/aarch64/aarch64-sve.md (add3, sub3) + (3, *add3, *mul3) + (*fabd3): Add more MOVPRFX alternatives. + 2019-08-15 Richard Sandiford Prathamesh Kulkarni diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index af68c17c989..c4e46025903 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1937,16 +1937,19 @@ ;; ------------------------------------------------------------------------- (define_insn "add3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, ?w, ?w, w") (plus:SVE_I - (match_operand:SVE_I 1 "register_operand" "%0, 0, 0, w") - (match_operand:SVE_I 2 "aarch64_sve_add_operand" "vsa, vsn, vsi, w")))] + (match_operand:SVE_I 1 "register_operand" "%0, 0, 0, w, w, w") + (match_operand:SVE_I 2 "aarch64_sve_add_operand" "vsa, vsn, vsi, vsa, vsn, w")))] "TARGET_SVE" "@ add\t%0., %0., #%D2 sub\t%0., %0., #%N2 * return aarch64_output_sve_inc_dec_immediate (\"%0.\", operands[2]); + movprfx\t%0, %1\;add\t%0., %0., #%D2 + movprfx\t%0, %1\;sub\t%0., %0., #%N2 add\t%0., %1., %2." + [(set_attr "movprfx" "*,*,*,yes,yes,*")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -1960,14 +1963,16 @@ ;; ------------------------------------------------------------------------- (define_insn "sub3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") (minus:SVE_I - (match_operand:SVE_I 1 "aarch64_sve_arith_operand" "w, vsa") - (match_operand:SVE_I 2 "register_operand" "w, 0")))] + (match_operand:SVE_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa") + (match_operand:SVE_I 2 "register_operand" "w, 0, w")))] "TARGET_SVE" "@ sub\t%0., %1., %2. - subr\t%0., %0., #%D1" + subr\t%0., %0., #%D1 + movprfx\t%0, %2\;subr\t%0., %0., #%D1" + [(set_attr "movprfx" "*,*,yes")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -2320,14 +2325,16 @@ ;; Unpredicated integer binary logical operations. (define_insn "3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?w, w") (LOGICAL:SVE_I - (match_operand:SVE_I 1 "register_operand" "%0, w") - (match_operand:SVE_I 2 "aarch64_sve_logical_operand" "vsl, w")))] + (match_operand:SVE_I 1 "register_operand" "%0, w, w") + (match_operand:SVE_I 2 "aarch64_sve_logical_operand" "vsl, vsl, w")))] "TARGET_SVE" "@ \t%0., %0., #%C2 + movprfx\t%0, %1\;\t%0., %0., #%C2 \t%0.d, %1.d, %2.d" + [(set_attr "movprfx" "*,yes,*")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -2773,23 +2780,27 @@ ;; Predicated floating-point addition. (define_insn_and_split "*add3" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, ?&w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, i, Z") - (match_operand:SVE_F 2 "register_operand" "%0, 0, w") - (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") + (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, i, Z, i, i") + (match_operand:SVE_F 2 "register_operand" "%0, 0, w, w, w") + (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, w, vsA, vsN")] UNSPEC_COND_FADD))] "TARGET_SVE" "@ fadd\t%0., %1/m, %0., #%3 fsub\t%0., %1/m, %0., #%N3 - #" + # + movprfx\t%0, %2\;fadd\t%0., %1/m, %0., #%3 + movprfx\t%0, %2\;fsub\t%0., %1/m, %0., #%N3" ; Split the unpredicated form after reload, so that we don't have ; the unnecessary PTRUE. "&& reload_completed && register_operand (operands[3], mode)" [(set (match_dup 0) (plus:SVE_F (match_dup 2) (match_dup 3)))] + "" + [(set_attr "movprfx" "*,*,*,yes,yes")] ) ;; Predicated floating-point addition of a constant, merging with the @@ -2972,23 +2983,26 @@ ;; Predicated floating-point absolute difference. (define_insn_and_rewrite "*fabd3" - [(set (match_operand:SVE_F 0 "register_operand" "=w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 4 "aarch64_sve_gp_strictness") (unspec:SVE_F [(match_operand 5) (match_operand:SI 6 "aarch64_sve_gp_strictness") - (match_operand:SVE_F 2 "register_operand" "0") - (match_operand:SVE_F 3 "register_operand" "w")] + (match_operand:SVE_F 2 "register_operand" "%0, w") + (match_operand:SVE_F 3 "register_operand" "w, w")] UNSPEC_COND_FSUB)] UNSPEC_COND_FABS))] "TARGET_SVE && aarch64_sve_pred_dominates_p (&operands[5], operands[1])" - "fabd\t%0., %1/m, %2., %3." + "@ + fabd\t%0., %1/m, %0., %3. + movprfx\t%0, %2\;fabd\t%0., %1/m, %0., %3." "&& !rtx_equal_p (operands[1], operands[5])" { operands[5] = copy_rtx (operands[1]); } + [(set_attr "movprfx" "*,yes")] ) ;; Predicated floating-point absolute difference, merging with the first @@ -3117,22 +3131,25 @@ ;; Predicated floating-point multiplication. (define_insn_and_split "*mul3" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") - (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, Z") - (match_operand:SVE_F 2 "register_operand" "%0, w") - (match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, Z, i") + (match_operand:SVE_F 2 "register_operand" "%0, w, 0") + (match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w, vsM")] UNSPEC_COND_FMUL))] "TARGET_SVE" "@ fmul\t%0., %1/m, %0., #%3 - #" + # + movprfx\t%0, %2\;fmul\t%0., %1/m, %0., #%3" ; Split the unpredicated form after reload, so that we don't have ; the unnecessary PTRUE. "&& reload_completed && register_operand (operands[3], mode)" [(set (match_dup 0) (mult:SVE_F (match_dup 2) (match_dup 3)))] + "" + [(set_attr "movprfx" "*,*,yes")] ) ;; Merging forms are handled through SVE_COND_FP_BINARY and -- 2.30.2