From 5e1f64305e028cd9fd7c8b5befb9d11934845cb8 Mon Sep 17 00:00:00 2001 From: Hans-Peter Nilsson Date: Mon, 21 Nov 2005 04:48:19 +0000 Subject: [PATCH] * sim/cris: New directory with C and assembly tests for the CRIS simulator. --- sim/testsuite/ChangeLog | 5 + sim/testsuite/sim/cris/asm/abs.ms | 50 +++ sim/testsuite/sim/cris/asm/addc.ms | 81 +++++ sim/testsuite/sim/cris/asm/addcpc.ms | 35 +++ sim/testsuite/sim/cris/asm/addcv32c.ms | 50 +++ sim/testsuite/sim/cris/asm/addcv32m.ms | 69 +++++ sim/testsuite/sim/cris/asm/addcv32r.ms | 57 ++++ sim/testsuite/sim/cris/asm/addi.ms | 57 ++++ sim/testsuite/sim/cris/asm/addiv32.ms | 62 ++++ sim/testsuite/sim/cris/asm/addm.ms | 96 ++++++ sim/testsuite/sim/cris/asm/addoc.ms | 44 +++ sim/testsuite/sim/cris/asm/addom.ms | 55 ++++ sim/testsuite/sim/cris/asm/addoq.ms | 31 ++ sim/testsuite/sim/cris/asm/addq.ms | 47 +++ sim/testsuite/sim/cris/asm/addqpc.ms | 8 + sim/testsuite/sim/cris/asm/addr.ms | 96 ++++++ sim/testsuite/sim/cris/asm/addswpc.ms | 61 ++++ sim/testsuite/sim/cris/asm/addxc.ms | 91 ++++++ sim/testsuite/sim/cris/asm/addxm.ms | 106 +++++++ sim/testsuite/sim/cris/asm/addxr.ms | 93 ++++++ sim/testsuite/sim/cris/asm/andc.ms | 80 +++++ sim/testsuite/sim/cris/asm/andm.ms | 90 ++++++ sim/testsuite/sim/cris/asm/andq.ms | 46 +++ sim/testsuite/sim/cris/asm/andr.ms | 95 ++++++ sim/testsuite/sim/cris/asm/asm.exp | 46 +++ sim/testsuite/sim/cris/asm/asr.ms | 228 ++++++++++++++ sim/testsuite/sim/cris/asm/ba.ms | 93 ++++++ sim/testsuite/sim/cris/asm/bare1.ms | 24 ++ sim/testsuite/sim/cris/asm/bare2.ms | 9 + sim/testsuite/sim/cris/asm/bas.ms | 102 +++++++ sim/testsuite/sim/cris/asm/bccb.ms | 181 +++++++++++ sim/testsuite/sim/cris/asm/bdapc.ms | 57 ++++ sim/testsuite/sim/cris/asm/bdapm.ms | 56 ++++ sim/testsuite/sim/cris/asm/bdapq.ms | 29 ++ sim/testsuite/sim/cris/asm/bdapqpc.ms | 30 ++ sim/testsuite/sim/cris/asm/biap.ms | 56 ++++ sim/testsuite/sim/cris/asm/boundc.ms | 101 +++++++ sim/testsuite/sim/cris/asm/boundm.ms | 105 +++++++ sim/testsuite/sim/cris/asm/boundmv32.ms | 15 + sim/testsuite/sim/cris/asm/boundr.ms | 125 ++++++++ sim/testsuite/sim/cris/asm/break.ms | 15 + sim/testsuite/sim/cris/asm/btst.ms | 87 ++++++ sim/testsuite/sim/cris/asm/ccr-v10.ms | 79 +++++ sim/testsuite/sim/cris/asm/ccs-v32.ms | 73 +++++ sim/testsuite/sim/cris/asm/clearfv10.ms | 12 + sim/testsuite/sim/cris/asm/clearfv32.ms | 12 + sim/testsuite/sim/cris/asm/clrjmp1.ms | 36 +++ sim/testsuite/sim/cris/asm/cmpc.ms | 86 ++++++ sim/testsuite/sim/cris/asm/cmpm.ms | 96 ++++++ sim/testsuite/sim/cris/asm/cmpq.ms | 75 +++++ sim/testsuite/sim/cris/asm/cmpr.ms | 102 +++++++ sim/testsuite/sim/cris/asm/cmpxc.ms | 92 ++++++ sim/testsuite/sim/cris/asm/cmpxm.ms | 106 +++++++ sim/testsuite/sim/cris/asm/dflags.ms | 62 ++++ sim/testsuite/sim/cris/asm/dip.ms | 41 +++ sim/testsuite/sim/cris/asm/dstep.ms | 42 +++ sim/testsuite/sim/cris/asm/fidxd.ms | 9 + sim/testsuite/sim/cris/asm/fidxi.ms | 9 + sim/testsuite/sim/cris/asm/ftagd.ms | 9 + sim/testsuite/sim/cris/asm/ftagi.ms | 9 + sim/testsuite/sim/cris/asm/halt.ms | 9 + sim/testsuite/sim/cris/asm/io1.ms | 8 + sim/testsuite/sim/cris/asm/io2.ms | 18 ++ sim/testsuite/sim/cris/asm/io3.ms | 17 ++ sim/testsuite/sim/cris/asm/io4.ms | 18 ++ sim/testsuite/sim/cris/asm/io5.ms | 17 ++ sim/testsuite/sim/cris/asm/io6.ms | 22 ++ sim/testsuite/sim/cris/asm/io7.ms | 22 ++ sim/testsuite/sim/cris/asm/io8.ms | 21 ++ sim/testsuite/sim/cris/asm/io9.ms | 21 ++ sim/testsuite/sim/cris/asm/jsr.ms | 85 ++++++ sim/testsuite/sim/cris/asm/jsrmv10.ms | 40 +++ sim/testsuite/sim/cris/asm/jumpmp.ms | 21 ++ sim/testsuite/sim/cris/asm/jumppv32.ms | 28 ++ sim/testsuite/sim/cris/asm/lapc.ms | 78 +++++ sim/testsuite/sim/cris/asm/lsl.ms | 217 +++++++++++++ sim/testsuite/sim/cris/asm/lsr.ms | 217 +++++++++++++ sim/testsuite/sim/cris/asm/lz.ms | 52 ++++ sim/testsuite/sim/cris/asm/mcp.ms | 49 +++ sim/testsuite/sim/cris/asm/movdelsr1.ms | 33 ++ sim/testsuite/sim/cris/asm/movecpc.ms | 19 ++ sim/testsuite/sim/cris/asm/movecr.ms | 37 +++ sim/testsuite/sim/cris/asm/movecrt10.ms | 17 ++ sim/testsuite/sim/cris/asm/movecrt32.ms | 14 + sim/testsuite/sim/cris/asm/movect10.ms | 18 ++ sim/testsuite/sim/cris/asm/movei.ms | 47 +++ sim/testsuite/sim/cris/asm/movempc.ms | 8 + sim/testsuite/sim/cris/asm/movemr.ms | 79 +++++ sim/testsuite/sim/cris/asm/movemrv10.ms | 101 +++++++ sim/testsuite/sim/cris/asm/movemrv32.ms | 97 ++++++ sim/testsuite/sim/cris/asm/movepcb.ms | 9 + sim/testsuite/sim/cris/asm/movepcd.ms | 16 + sim/testsuite/sim/cris/asm/movepcw.ms | 9 + sim/testsuite/sim/cris/asm/moveq.ms | 15 + sim/testsuite/sim/cris/asm/moveqpc.ms | 9 + sim/testsuite/sim/cris/asm/mover.ms | 29 ++ sim/testsuite/sim/cris/asm/moverbpc.ms | 9 + sim/testsuite/sim/cris/asm/moverdpc.ms | 9 + sim/testsuite/sim/cris/asm/moverm.ms | 45 +++ sim/testsuite/sim/cris/asm/moverpcb.ms | 9 + sim/testsuite/sim/cris/asm/moverpcd.ms | 13 + sim/testsuite/sim/cris/asm/moverpcw.ms | 9 + sim/testsuite/sim/cris/asm/moverwpc.ms | 9 + sim/testsuite/sim/cris/asm/movesmp.ms | 28 ++ sim/testsuite/sim/cris/asm/movmp.ms | 116 +++++++ sim/testsuite/sim/cris/asm/movpmv10.ms | 35 +++ sim/testsuite/sim/cris/asm/movpmv32.ms | 35 +++ sim/testsuite/sim/cris/asm/movppc.ms | 7 + sim/testsuite/sim/cris/asm/movpr.ms | 28 ++ sim/testsuite/sim/cris/asm/movprv10.ms | 21 ++ sim/testsuite/sim/cris/asm/movprv32.ms | 21 ++ sim/testsuite/sim/cris/asm/movrss.ms | 8 + sim/testsuite/sim/cris/asm/movscpc.ms | 13 + sim/testsuite/sim/cris/asm/movscr.ms | 29 ++ sim/testsuite/sim/cris/asm/movsm.ms | 44 +++ sim/testsuite/sim/cris/asm/movsmpc.ms | 8 + sim/testsuite/sim/cris/asm/movsr.ms | 46 +++ sim/testsuite/sim/cris/asm/movsrpc.ms | 9 + sim/testsuite/sim/cris/asm/movssr.ms | 8 + sim/testsuite/sim/cris/asm/movucpc.ms | 10 + sim/testsuite/sim/cris/asm/movucr.ms | 33 ++ sim/testsuite/sim/cris/asm/movum.ms | 40 +++ sim/testsuite/sim/cris/asm/movumpc.ms | 8 + sim/testsuite/sim/cris/asm/movur.ms | 45 +++ sim/testsuite/sim/cris/asm/movurpc.ms | 9 + sim/testsuite/sim/cris/asm/mstep.ms | 108 +++++++ sim/testsuite/sim/cris/asm/msteppc1.ms | 8 + sim/testsuite/sim/cris/asm/msteppc2.ms | 8 + sim/testsuite/sim/cris/asm/msteppc3.ms | 8 + sim/testsuite/sim/cris/asm/mulv10.ms | 29 ++ sim/testsuite/sim/cris/asm/mulv32.ms | 51 ++++ sim/testsuite/sim/cris/asm/mulx.ms | 246 +++++++++++++++ sim/testsuite/sim/cris/asm/neg.ms | 102 +++++++ sim/testsuite/sim/cris/asm/nopv10t.ms | 13 + sim/testsuite/sim/cris/asm/nopv32t.ms | 21 ++ sim/testsuite/sim/cris/asm/nopv32t2.ms | 13 + sim/testsuite/sim/cris/asm/nopv32t3.ms | 13 + sim/testsuite/sim/cris/asm/nopv32t4.ms | 13 + sim/testsuite/sim/cris/asm/not.ms | 31 ++ sim/testsuite/sim/cris/asm/op3.ms | 98 ++++++ sim/testsuite/sim/cris/asm/opterr1.ms | 5 + sim/testsuite/sim/cris/asm/opterr2.ms | 5 + sim/testsuite/sim/cris/asm/option1.ms | 7 + sim/testsuite/sim/cris/asm/option2.ms | 5 + sim/testsuite/sim/cris/asm/orc.ms | 71 +++++ sim/testsuite/sim/cris/asm/orm.ms | 75 +++++ sim/testsuite/sim/cris/asm/orq.ms | 41 +++ sim/testsuite/sim/cris/asm/orr.ms | 84 +++++ sim/testsuite/sim/cris/asm/raw1.ms | 22 ++ sim/testsuite/sim/cris/asm/raw10.ms | 22 ++ sim/testsuite/sim/cris/asm/raw11.ms | 23 ++ sim/testsuite/sim/cris/asm/raw12.ms | 24 ++ sim/testsuite/sim/cris/asm/raw13.ms | 22 ++ sim/testsuite/sim/cris/asm/raw14.ms | 14 + sim/testsuite/sim/cris/asm/raw15.ms | 14 + sim/testsuite/sim/cris/asm/raw16.ms | 14 + sim/testsuite/sim/cris/asm/raw17.ms | 29 ++ sim/testsuite/sim/cris/asm/raw2.ms | 22 ++ sim/testsuite/sim/cris/asm/raw3.ms | 22 ++ sim/testsuite/sim/cris/asm/raw4.ms | 22 ++ sim/testsuite/sim/cris/asm/raw5.ms | 23 ++ sim/testsuite/sim/cris/asm/raw6.ms | 24 ++ sim/testsuite/sim/cris/asm/raw7.ms | 25 ++ sim/testsuite/sim/cris/asm/raw8.ms | 26 ++ sim/testsuite/sim/cris/asm/raw9.ms | 27 ++ sim/testsuite/sim/cris/asm/ret.ms | 25 ++ sim/testsuite/sim/cris/asm/rfe.ms | 47 +++ sim/testsuite/sim/cris/asm/rfg.ms | 9 + sim/testsuite/sim/cris/asm/rfn.ms | 53 ++++ sim/testsuite/sim/cris/asm/sbfs.ms | 7 + sim/testsuite/sim/cris/asm/scc.ms | 89 ++++++ sim/testsuite/sim/cris/asm/sfe.ms | 51 ++++ sim/testsuite/sim/cris/asm/subc.ms | 86 ++++++ sim/testsuite/sim/cris/asm/subm.ms | 96 ++++++ sim/testsuite/sim/cris/asm/subq.ms | 52 ++++ sim/testsuite/sim/cris/asm/subqpc.ms | 8 + sim/testsuite/sim/cris/asm/subr.ms | 102 +++++++ sim/testsuite/sim/cris/asm/subxc.ms | 92 ++++++ sim/testsuite/sim/cris/asm/subxm.ms | 106 +++++++ sim/testsuite/sim/cris/asm/subxr.ms | 108 +++++++ sim/testsuite/sim/cris/asm/swap.ms | 87 ++++++ sim/testsuite/sim/cris/asm/tb.ms | 72 +++++ sim/testsuite/sim/cris/asm/test.ms | 80 +++++ sim/testsuite/sim/cris/asm/testutils.inc | 353 ++++++++++++++++++++++ sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms | 55 ++++ sim/testsuite/sim/cris/asm/tjmpsrv32.ms | 50 +++ sim/testsuite/sim/cris/asm/tjsrcv10.ms | 29 ++ sim/testsuite/sim/cris/asm/tjsrcv32.ms | 13 + sim/testsuite/sim/cris/asm/tmemv10.ms | 27 ++ sim/testsuite/sim/cris/asm/tmemv32.ms | 14 + sim/testsuite/sim/cris/asm/tmulv10.ms | 26 ++ sim/testsuite/sim/cris/asm/tmulv32.ms | 14 + sim/testsuite/sim/cris/asm/tmvm1.ms | 53 ++++ sim/testsuite/sim/cris/asm/tmvm2.ms | 351 +++++++++++++++++++++ sim/testsuite/sim/cris/asm/tmvmrv10.ms | 50 +++ sim/testsuite/sim/cris/asm/tmvmrv32.ms | 14 + sim/testsuite/sim/cris/asm/tmvrmv10.ms | 40 +++ sim/testsuite/sim/cris/asm/tmvrmv32.ms | 14 + sim/testsuite/sim/cris/asm/user.ms | 75 +++++ sim/testsuite/sim/cris/asm/x0-v10.ms | 7 + sim/testsuite/sim/cris/asm/x0-v32.ms | 7 + sim/testsuite/sim/cris/asm/x1-v10.ms | 8 + sim/testsuite/sim/cris/asm/x1-v32.ms | 8 + sim/testsuite/sim/cris/asm/x10-v10.ms | 21 ++ sim/testsuite/sim/cris/asm/x2-v10.ms | 59 ++++ sim/testsuite/sim/cris/asm/x2-v32.ms | 59 ++++ sim/testsuite/sim/cris/asm/x3-v10.ms | 10 + sim/testsuite/sim/cris/asm/x3-v32.ms | 10 + sim/testsuite/sim/cris/asm/x4-v32.ms | 23 ++ sim/testsuite/sim/cris/asm/x5-v10.ms | 9 + sim/testsuite/sim/cris/asm/x5-v32.ms | 9 + sim/testsuite/sim/cris/asm/x6-v10.ms | 11 + sim/testsuite/sim/cris/asm/x6-v32.ms | 11 + sim/testsuite/sim/cris/asm/x7-v10.ms | 29 ++ sim/testsuite/sim/cris/asm/x7-v32.ms | 19 ++ sim/testsuite/sim/cris/asm/x8-v10.ms | 20 ++ sim/testsuite/sim/cris/asm/x9-v10.ms | 23 ++ sim/testsuite/sim/cris/asm/xor.ms | 47 +++ sim/testsuite/sim/cris/c/append1.c | 51 ++++ sim/testsuite/sim/cris/c/c.exp | 211 +++++++++++++ sim/testsuite/sim/cris/c/clone1.c | 90 ++++++ sim/testsuite/sim/cris/c/clone2.c | 6 + sim/testsuite/sim/cris/c/clone3.c | 45 +++ sim/testsuite/sim/cris/c/clone4.c | 61 ++++ sim/testsuite/sim/cris/c/clone5.c | 32 ++ sim/testsuite/sim/cris/c/ex1.c | 54 ++++ sim/testsuite/sim/cris/c/fcntl1.c | 16 + sim/testsuite/sim/cris/c/fdopen1.c | 54 ++++ sim/testsuite/sim/cris/c/fdopen2.c | 52 ++++ sim/testsuite/sim/cris/c/freopen1.c | 52 ++++ sim/testsuite/sim/cris/c/ftruncate1.c | 52 ++++ sim/testsuite/sim/cris/c/ftruncate2.c | 39 +++ sim/testsuite/sim/cris/c/getcwd1.c | 18 ++ sim/testsuite/sim/cris/c/gettod.c | 27 ++ sim/testsuite/sim/cris/c/hello.c | 7 + sim/testsuite/sim/cris/c/kill1.c | 30 ++ sim/testsuite/sim/cris/c/kill2.c | 16 + sim/testsuite/sim/cris/c/kill3.c | 16 + sim/testsuite/sim/cris/c/mapbrk.c | 39 +++ sim/testsuite/sim/cris/c/mmap1.c | 48 +++ sim/testsuite/sim/cris/c/mmap2.c | 48 +++ sim/testsuite/sim/cris/c/mmap3.c | 33 ++ sim/testsuite/sim/cris/c/mprotect1.c | 16 + sim/testsuite/sim/cris/c/mremap.c | 31 ++ sim/testsuite/sim/cris/c/openpf1.c | 38 +++ sim/testsuite/sim/cris/c/openpf2.c | 16 + sim/testsuite/sim/cris/c/openpf3.c | 49 +++ sim/testsuite/sim/cris/c/openpf4.c | 5 + sim/testsuite/sim/cris/c/openpf5.c | 56 ++++ sim/testsuite/sim/cris/c/pipe1.c | 47 +++ sim/testsuite/sim/cris/c/pipe2.c | 124 ++++++++ sim/testsuite/sim/cris/c/pipe3.c | 48 +++ sim/testsuite/sim/cris/c/pipe4.c | 66 ++++ sim/testsuite/sim/cris/c/pipe5.c | 59 ++++ sim/testsuite/sim/cris/c/pipe6.c | 111 +++++++ sim/testsuite/sim/cris/c/pipe7.c | 21 ++ sim/testsuite/sim/cris/c/readlink1.c | 20 ++ sim/testsuite/sim/cris/c/readlink10.c | 18 ++ sim/testsuite/sim/cris/c/readlink2.c | 73 +++++ sim/testsuite/sim/cris/c/readlink3.c | 6 + sim/testsuite/sim/cris/c/readlink4.c | 62 ++++ sim/testsuite/sim/cris/c/readlink5.c | 8 + sim/testsuite/sim/cris/c/readlink6.c | 5 + sim/testsuite/sim/cris/c/readlink7.c | 6 + sim/testsuite/sim/cris/c/readlink8.c | 8 + sim/testsuite/sim/cris/c/readlink9.c | 23 ++ sim/testsuite/sim/cris/c/rename2.c | 38 +++ sim/testsuite/sim/cris/c/rtsigprocmask1.c | 45 +++ sim/testsuite/sim/cris/c/rtsigsuspend1.c | 18 ++ sim/testsuite/sim/cris/c/sched1.c | 15 + sim/testsuite/sim/cris/c/sched2.c | 19 ++ sim/testsuite/sim/cris/c/sched3.c | 24 ++ sim/testsuite/sim/cris/c/sched4.c | 24 ++ sim/testsuite/sim/cris/c/sched5.c | 19 ++ sim/testsuite/sim/cris/c/sched6.c | 15 + sim/testsuite/sim/cris/c/sched7.c | 17 ++ sim/testsuite/sim/cris/c/sched8.c | 19 ++ sim/testsuite/sim/cris/c/sched9.c | 24 ++ sim/testsuite/sim/cris/c/seek1.c | 47 +++ sim/testsuite/sim/cris/c/seek2.c | 4 + sim/testsuite/sim/cris/c/setrlimit1.c | 22 ++ sim/testsuite/sim/cris/c/sig1.c | 20 ++ sim/testsuite/sim/cris/c/sig10.c | 33 ++ sim/testsuite/sim/cris/c/sig11.c | 32 ++ sim/testsuite/sim/cris/c/sig12.c | 38 +++ sim/testsuite/sim/cris/c/sig2.c | 32 ++ sim/testsuite/sim/cris/c/sig3.c | 13 + sim/testsuite/sim/cris/c/sig4.c | 30 ++ sim/testsuite/sim/cris/c/sig5.c | 16 + sim/testsuite/sim/cris/c/sig6.c | 32 ++ sim/testsuite/sim/cris/c/sig7.c | 24 ++ sim/testsuite/sim/cris/c/sig8.c | 19 ++ sim/testsuite/sim/cris/c/sig9.c | 36 +++ sim/testsuite/sim/cris/c/sigreturn1.c | 18 ++ sim/testsuite/sim/cris/c/sigreturn2.c | 33 ++ sim/testsuite/sim/cris/c/sjlj.c | 34 +++ sim/testsuite/sim/cris/c/sock1.c | 32 ++ sim/testsuite/sim/cris/c/stat1.c | 16 + sim/testsuite/sim/cris/c/stat2.c | 20 ++ sim/testsuite/sim/cris/c/stat3.c | 26 ++ sim/testsuite/sim/cris/c/stat4.c | 28 ++ sim/testsuite/sim/cris/c/stat5.c | 20 ++ sim/testsuite/sim/cris/c/stat7.c | 26 ++ sim/testsuite/sim/cris/c/stat8.c | 26 ++ sim/testsuite/sim/cris/c/syscall1.c | 19 ++ sim/testsuite/sim/cris/c/syscall2.c | 18 ++ sim/testsuite/sim/cris/c/sysctl1.c | 38 +++ sim/testsuite/sim/cris/c/sysctl2.c | 38 +++ sim/testsuite/sim/cris/c/thread2.c | 28 ++ sim/testsuite/sim/cris/c/thread3.c | 46 +++ sim/testsuite/sim/cris/c/thread4.c | 50 +++ sim/testsuite/sim/cris/c/thread5.c | 77 +++++ sim/testsuite/sim/cris/c/time1.c | 46 +++ sim/testsuite/sim/cris/c/truncate1.c | 49 +++ sim/testsuite/sim/cris/c/truncate2.c | 6 + sim/testsuite/sim/cris/c/ugetrlimit1.c | 21 ++ 316 files changed, 13606 insertions(+) create mode 100644 sim/testsuite/sim/cris/asm/abs.ms create mode 100644 sim/testsuite/sim/cris/asm/addc.ms create mode 100644 sim/testsuite/sim/cris/asm/addcpc.ms create mode 100644 sim/testsuite/sim/cris/asm/addcv32c.ms create mode 100644 sim/testsuite/sim/cris/asm/addcv32m.ms create mode 100644 sim/testsuite/sim/cris/asm/addcv32r.ms create mode 100644 sim/testsuite/sim/cris/asm/addi.ms create mode 100644 sim/testsuite/sim/cris/asm/addiv32.ms create mode 100644 sim/testsuite/sim/cris/asm/addm.ms create mode 100644 sim/testsuite/sim/cris/asm/addoc.ms create mode 100644 sim/testsuite/sim/cris/asm/addom.ms create mode 100644 sim/testsuite/sim/cris/asm/addoq.ms create mode 100644 sim/testsuite/sim/cris/asm/addq.ms create mode 100644 sim/testsuite/sim/cris/asm/addqpc.ms create mode 100644 sim/testsuite/sim/cris/asm/addr.ms create mode 100644 sim/testsuite/sim/cris/asm/addswpc.ms create mode 100644 sim/testsuite/sim/cris/asm/addxc.ms create mode 100644 sim/testsuite/sim/cris/asm/addxm.ms create mode 100644 sim/testsuite/sim/cris/asm/addxr.ms create mode 100644 sim/testsuite/sim/cris/asm/andc.ms create mode 100644 sim/testsuite/sim/cris/asm/andm.ms create mode 100644 sim/testsuite/sim/cris/asm/andq.ms create mode 100644 sim/testsuite/sim/cris/asm/andr.ms create mode 100644 sim/testsuite/sim/cris/asm/asm.exp create mode 100644 sim/testsuite/sim/cris/asm/asr.ms create mode 100644 sim/testsuite/sim/cris/asm/ba.ms create mode 100644 sim/testsuite/sim/cris/asm/bare1.ms create mode 100644 sim/testsuite/sim/cris/asm/bare2.ms create mode 100644 sim/testsuite/sim/cris/asm/bas.ms create mode 100644 sim/testsuite/sim/cris/asm/bccb.ms create mode 100644 sim/testsuite/sim/cris/asm/bdapc.ms create mode 100644 sim/testsuite/sim/cris/asm/bdapm.ms create mode 100644 sim/testsuite/sim/cris/asm/bdapq.ms create mode 100644 sim/testsuite/sim/cris/asm/bdapqpc.ms create mode 100644 sim/testsuite/sim/cris/asm/biap.ms create mode 100644 sim/testsuite/sim/cris/asm/boundc.ms create mode 100644 sim/testsuite/sim/cris/asm/boundm.ms create mode 100644 sim/testsuite/sim/cris/asm/boundmv32.ms create mode 100644 sim/testsuite/sim/cris/asm/boundr.ms create mode 100644 sim/testsuite/sim/cris/asm/break.ms create mode 100644 sim/testsuite/sim/cris/asm/btst.ms create mode 100644 sim/testsuite/sim/cris/asm/ccr-v10.ms create mode 100644 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mode 100644 sim/testsuite/sim/cris/c/truncate1.c create mode 100644 sim/testsuite/sim/cris/c/truncate2.c create mode 100644 sim/testsuite/sim/cris/c/ugetrlimit1.c diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index c86d915d4a4..2b794d5477b 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2005-11-21 Hans-Peter Nilsson + + * sim/cris: New directory with C and assembly tests for the CRIS + simulator. + 2005-01-11 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/testsuite/sim/cris/asm/abs.ms b/sim/testsuite/sim/cris/asm/abs.ms new file mode 100644 index 00000000000..a428434982e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/abs.ms @@ -0,0 +1,50 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n0\n80000000\n7fffffff\n2a\n1\nffff\n1f\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 0,r3 + dumpr3 ; 0 + + move.d 0x80000000,r4 + abs r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + move.d 0x7fffffff,r4 + abs r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7fffffff + + move.d 42,r3 + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2a + + moveq 1,r6 + abs r6,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + abs r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -31,r5 + abs r5,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq 0,r5 + abs r5,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/addc.ms b/sim/testsuite/sim/cris/asm/addc.ms new file mode 100644 index 00000000000..8b7fa72e20e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addc.ms @@ -0,0 +1,81 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n + + .include "testutils.inc" + start + moveq -1,r3 + add.d 2,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + add.d -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.d 0xffff,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r3 + add.d -1,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + add.d 0x5432f789,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + add.w 2,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + add.w -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + add.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + add.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + add.b 2,r3 + test_cc 0 0 0 1 + dumpr3 ; ffffff01 + + moveq 2,r3 + add.b -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r3 + add.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + add.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + add.b 0x89,r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/sim/cris/asm/addcpc.ms b/sim/testsuite/sim/cris/asm/addcpc.ms new file mode 100644 index 00000000000..0302fa20362 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addcpc.ms @@ -0,0 +1,35 @@ +# mach: crisv3 crisv8 crisv10 +# output: 2f\n31\n + +# Test that the special case add.d const,pc works. + + .include "testutils.inc" + start +x: + add.d y-y0,pc +y0: + quit + + .space 1000 + quit + quit + quit + quit + quit +z: + move.d 49,r3 + dumpr3 + quit + + .space 1000 + quit + quit + quit + quit + quit +y: + move.d 47,r3 + dumpr3 + add.d z-z0,pc +z0: + quit diff --git a/sim/testsuite/sim/cris/asm/addcv32c.ms b/sim/testsuite/sim/cris/asm/addcv32c.ms new file mode 100644 index 00000000000..0264fae9131 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addcv32c.ms @@ -0,0 +1,50 @@ +# mach: crisv32 +# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + start + clearf cz + moveq 0,r3 + addc 0,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + addc 0,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf cz + moveq 0,r3 + addc 0,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq -1,r3 + addc 2,r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + addc -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r3 + addc 0xffff,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r3 + addc -1,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x78134452,r3 + addc 0x5432f789,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/sim/cris/asm/addcv32m.ms b/sim/testsuite/sim/cris/asm/addcv32m.ms new file mode 100644 index 00000000000..13139b2f457 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addcv32m.ms @@ -0,0 +1,69 @@ +# mach: crisv32 +# output: 0\n0\n1\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + .data +x: + .dword 0,0,2,-1,0xffff,-1,0x5432f789 + + start + move.d x,r5 + clearf cz + moveq 0,r3 + addc [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + addc [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf c + moveq 0,r3 + addc [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq 0,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf c + moveq 0,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + clearf c + moveq -1,r3 + addc [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + addc [r5],r3 + moveq 4,r6 + addi r6.b,r5 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r3 + addc [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r3 + addc [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x78134452,r3 + addc [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/sim/cris/asm/addcv32r.ms b/sim/testsuite/sim/cris/asm/addcv32r.ms new file mode 100644 index 00000000000..20aeb12ccae --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addcv32r.ms @@ -0,0 +1,57 @@ +# mach: crisv32 +# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n + + .include "testutils.inc" + start + clearf cz + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + setf z + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + setf cz + moveq 0,r3 + moveq 0,r4 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 2,r4 + addc r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1+c + + moveq 2,r3 + moveq -1,r4 + addc r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 2+c + + move.d 0xffff,r4 + move.d r4,r3 + addc r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + moveq -1,r4 + move.d r4,r3 + addc r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe+c + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addc r4,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + quit diff --git a/sim/testsuite/sim/cris/asm/addi.ms b/sim/testsuite/sim/cris/asm/addi.ms new file mode 100644 index 00000000000..2fa2723ef82 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addi.ms @@ -0,0 +1,57 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n + + .include "testutils.inc" + start + moveq 0,r3 + moveq 0,r4 + clearf zcvn + addi r4.b,r3 + test_cc 0 0 0 0 + dumpr3 ; 0 + + moveq 0,r3 + moveq 1,r4 + setf zcvn + addi r4.b,r3 + test_cc 1 1 1 1 + dumpr3 ; 1 + + moveq 0,r3 + moveq 1,r4 + setf cv + clearf zn + addi r4.w,r3 + test_cc 0 0 1 1 + dumpr3 ; 2 + + moveq 0,r3 + moveq 1,r4 + clearf cv + setf zn + addi r4.d,r3 + test_cc 1 1 0 0 + dumpr3 ; 4 + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + clearf cn + setf zv + addi r4.b,r3 + test_cc 0 1 1 0 + dumpr3 ; be02460f + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + setf cn + clearf zv + addi r4.w,r3 + test_cc 1 0 0 1 + dumpr3 ; 69d035a6 + + move.d 0x12345678,r3 + move.d 0xabcdef97,r4 + addi r4.d,r3 + dumpr3 ; c16c14d4 + + quit diff --git a/sim/testsuite/sim/cris/asm/addiv32.ms b/sim/testsuite/sim/cris/asm/addiv32.ms new file mode 100644 index 00000000000..8040afcfdbb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addiv32.ms @@ -0,0 +1,62 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + setf cv + moveq -1,r0 + move.d x-32768,r5 + move.d 32769,r6 + addi r6.b,r5,acr + test_cc 0 0 1 1 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32771,r5 + setf znvc + moveq -1,r8 + addi r8.w,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + moveq 5,r10 + clearf znvc + addi r10.b,acr,acr + test_cc 0 0 0 0 + move.d [acr],r3 + dumpr3 ; ee19ccff + + subq 1,r5 + move.d r5,r8 + subq 1,r8 + moveq 1,r9 + addi r9.d,r8,acr + test_cc 0 0 0 0 + movu.w [acr],r3 + dumpr3 ; ff22 + + moveq -2,r11 + addi r11.w,acr,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + moveq 5,r9 + addi r9.d,acr,acr + subq 18,acr + move.d [acr],r3 + dumpr3 ; ff224455 + + move.d -76789888/4,r12 + addi r12.d,r5,acr + add.d 76789886,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/addm.ms b/sim/testsuite/sim/cris/asm/addm.ms new file mode 100644 index 00000000000..c214e3a2669 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,-1,0xffff,0xf789 + .byte 2,0xff,0x89 + .byte 0x7e + + start + moveq -1,r3 + move.d x,r5 + add.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + add.d [r5],r3 + test_cc 0 0 0 1 + addq 4,r5 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r3 + add.d [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + add.d [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r3 + add.w [r5],r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + add.w [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + add.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + add.b [r5],r3 + test_cc 0 0 0 1 + addq 1,r5 + dumpr3 ; ffffff01 + + moveq 2,r3 + add.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r3 + add.b [r5],r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + add.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + add.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + add.b [r5],r3 + test_cc 1 0 1 0 + dumpr3 ; 781344d0 + + quit diff --git a/sim/testsuite/sim/cris/asm/addoc.ms b/sim/testsuite/sim/cris/asm/addoc.ms new file mode 100644 index 00000000000..fe269d21ffc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addoc.ms @@ -0,0 +1,44 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + moveq -1,r0 + move.d x-32768,r5 + addo.d 32769,r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + addo.w -1,r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.d 5,acr,acr + move.d [acr],r3 + dumpr3 ; ee19ccff + + addo.b 3,r5,acr + movu.w [acr],r3 + dumpr3 ; ff22 + + addo.b -4,acr,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.w 2,acr,acr + move.d [acr],r3 + dumpr3 ; ff224455 + + addo.d -76789887,r5,acr + add.d 76789885,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/addom.ms b/sim/testsuite/sim/cris/asm/addom.ms new file mode 100644 index 00000000000..4e4ebb16a81 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addom.ms @@ -0,0 +1,55 @@ +# mach: crisv32 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 +y: + .dword 32769 + .word -1 + .dword 5 + .byte 3,-4 + .word 2 + .dword -76789887 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d y,r13 + addo.d [r13+],r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + addo.w [r13+],r5,acr + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.d [r13],acr,acr + addq 4,r13 + move.d [acr],r3 + dumpr3 ; ee19ccff + + addo.b [r13+],r5,acr + movu.w [acr],r3 + dumpr3 ; ff22 + + addo.b [r13],acr,acr + addq 1,r13 + move.d [acr],r3 + dumpr3 ; 4455aa77 + + addo.w [r13],acr,acr + addq 2,r13 + move.d [acr],r3 + dumpr3 ; ff224455 + + addo.d [r13+],r5,acr + add.d 76789885,acr + move.d [acr],r3 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/addoq.ms b/sim/testsuite/sim/cris/asm/addoq.ms new file mode 100644 index 00000000000..f4b6083d064 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addoq.ms @@ -0,0 +1,31 @@ +# mach: crisv32 +# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + start + moveq -1,r0 + move.d x+4,r5 + setf zvnc + addoq 0,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; ccff2244 + setf zvnc + addoq 4,r5,acr + test_cc 1 1 1 1 + move.d [acr],r3 + dumpr3 ; 88ccee19 + clearf zvnc + addoq -8,acr,acr + test_cc 0 0 0 0 + move.d [acr],r3 + dumpr3 ; 55aa77ff + addoq 3,r5,acr + movu.w [acr],r3 + dumpr3 ; 19cc + quit diff --git a/sim/testsuite/sim/cris/asm/addq.ms b/sim/testsuite/sim/cris/asm/addq.ms new file mode 100644 index 00000000000..6a27ac59531 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addq.ms @@ -0,0 +1,47 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n + + .include "testutils.inc" + start + moveq -2,r3 + addq 1,r3 + test_cc 1 0 0 0 + dumpr3 + + addq 1,r3 + test_cc 0 1 0 1 + dumpr3 + + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0xff,r3 + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0xffff,r3 + addq 1,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0x42,r3 + addq 5,r3 + test_cc 0 0 0 0 + dumpr3 + + addq 32,r3 + test_cc 0 0 0 0 + dumpr3 + + addq 63,r3 + test_cc 0 0 0 0 + dumpr3 + + move.d 0x7ffffffe,r3 + addq 3,r3 + test_cc 1 0 1 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/addqpc.ms b/sim/testsuite/sim/cris/asm/addqpc.ms new file mode 100644 index 00000000000..13e293e07ac --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addqpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + addq 1,pc + diff --git a/sim/testsuite/sim/cris/asm/addr.ms b/sim/testsuite/sim/cris/asm/addr.ms new file mode 100644 index 00000000000..c1b9348cbfb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addr.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + add.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + moveq -1,r4 + add.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + add.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + moveq -1,r4 + move.d r4,r3 + add.d r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.d r4,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdb + + moveq -1,r3 + moveq 2,r4 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff0001 + + moveq 2,r3 + moveq -1,r4 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + add.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffe + + move.d 0xfedaffff,r4 + move.d r4,r3 + add.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fedafffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + moveq -1,r3 + moveq 2,r4 + add.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffffff01 + + moveq 2,r3 + moveq -1,r4 + add.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + move.d 0xff,r4 + move.d r4,r3 + add.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fe + + move.d 0xfeda49ff,r4 + move.d r4,r3 + add.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; feda49fe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + add.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/sim/cris/asm/addswpc.ms b/sim/testsuite/sim/cris/asm/addswpc.ms new file mode 100644 index 00000000000..a7ac754caac --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addswpc.ms @@ -0,0 +1,61 @@ +# mach: crisv3 crisv8 crisv10 +# output: 7\n + +# Test that the special case adds.w [pc+rN.w],pc works. + + .include "testutils.inc" + start +x: + moveq 0,r3 + ba xy + moveq 5,r2 + +ok: + moveq 7,r3 + dumpr3 + quit + +xy: + adds.w [pc+r2.w],pc +y: + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word ok-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y + .word x0-y +x0: + quit diff --git a/sim/testsuite/sim/cris/asm/addxc.ms b/sim/testsuite/sim/cris/asm/addxc.ms new file mode 100644 index 00000000000..0e346dfd116 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addxc.ms @@ -0,0 +1,91 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + start + moveq 2,r3 + adds.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + adds.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + addu.b 0xff,r3 + dumpr3 ; 101 + + moveq 2,r3 + move.d 0xffffffff,r4 + addu.w -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 10001 + + move.d 0xffff,r3 + addu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 100fe + + move.d 0xffff,r3 + addu.w -1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + adds.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + move.d 0xffff,r3 + adds.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + moveq -1,r3 + adds.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + moveq -1,r3 + adds.w 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; fe + + moveq -1,r3 + adds.w 0xffff,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + addu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + adds.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 781343db + + move.d 0x78134452,r3 + addu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78143bdb + + move.d 0x78134452,r3 + adds.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + addu.b 0xff,r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + adds.w 0xffff,r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/addxm.ms b/sim/testsuite/sim/cris/asm/addxm.ms new file mode 100644 index 00000000000..40ae9aaea73 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .byte 0xff + .word 0xffff + + start + moveq 2,r3 + move.d x,r5 + adds.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + moveq 2,r3 + subq 3,r5 + addu.b [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 101 + + moveq 2,r3 + addu.w [r5+],r3 + subq 3,r5 + test_cc 0 0 0 0 + dumpr3 ; 10001 + + move.d 0xffff,r3 + addu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 100fe + + move.d 0xffff,r3 + addu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + adds.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + move.d 0xffff,r3 + adds.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; fffe + + moveq -1,r3 + adds.b [r5],r3 + test_cc 1 0 0 1 + addq 3,r5 + dumpr3 ; fffffffe + + moveq -1,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; fe + + moveq -1,r3 + adds.w [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + addu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 781344db + + move.d 0x78134452,r3 + adds.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 781343db + + move.d 0x78134452,r3 + addu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78143bdb + + move.d 0x78134452,r3 + adds.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + addu.b [r5+],r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + adds.w [r5+],r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/addxr.ms b/sim/testsuite/sim/cris/asm/addxr.ms new file mode 100644 index 00000000000..8234ac31072 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/addxr.ms @@ -0,0 +1,93 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n + + .include "testutils.inc" + start + moveq 2,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; 1 + + moveq 2,r3 + move.d 0xffff,r4 + adds.w r4,r3 + dumpr3 ; 1 + + moveq 2,r3 + move.d 0xffff,r4 + addu.b r4,r3 + dumpr3 ; 101 + + moveq 2,r3 + move.d 0xffffffff,r4 + addu.w r4,r3 + dumpr3 ; 10001 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + addu.b r4,r3 + dumpr3 ; 100fe + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + addu.w r4,r3 + dumpr3 ; 1fffe + + move.d 0xffff,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; fffe + + move.d 0xffff,r4 + move.d r4,r3 + adds.w r4,r3 + dumpr3 ; fffe + + moveq -1,r3 + move.d 0xff,r4 + adds.b r4,r3 + dumpr3 ; fffffffe + + moveq -1,r3 + move.d 0xff,r4 + adds.w r4,r3 + dumpr3 ; fe + + moveq -1,r3 + move.d 0xffff,r4 + adds.w r4,r3 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addu.b r4,r3 + dumpr3 ; 781344db + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + adds.b r4,r3 + dumpr3 ; 781343db + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + addu.w r4,r3 + dumpr3 ; 78143bdb + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + adds.w r4,r3 + dumpr3 ; 78133bdb + + move.d 0x7fffffee,r3 + move.d 0xff,r4 + addu.b r4,r3 + test_cc 1 0 1 0 + dumpr3 ; 800000ed + + move.d 0x1,r3 + move.d 0xffff,r4 + adds.w r4,r3 + test_cc 0 1 0 1 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/andc.ms b/sim/testsuite/sim/cris/asm/andc.ms new file mode 100644 index 00000000000..e800a0a9506 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/andc.ms @@ -0,0 +1,80 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + start + moveq -1,r3 + and.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + and.d -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + and.d 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + and.d -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + and.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + and.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + and.w -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + and.w 0xffff,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + and.w 0xff5f,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x78134452,r3 + and.w 0xf789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + and.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff02 + + moveq 2,r3 + and.b -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfa7,r3 + and.b 0x5a,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x78134453,r3 + and.b 0x89,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + and.b 0,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/sim/cris/asm/andm.ms b/sim/testsuite/sim/cris/asm/andm.ms new file mode 100644 index 00000000000..4e1a34bd050 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/andm.ms @@ -0,0 +1,90 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,-1,0xffff,0xff5f,0xf789 + .byte 2,-1,0x5a,0x89,0 + + start + moveq -1,r3 + move.d x,r5 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + and.d [r5],r3 + test_move_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + and.d [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + and.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + and.w [r5],r3 + test_move_cc 1 0 0 0 + addq 2,r5 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + and.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x78134452,r3 + and.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + and.b [r5],r3 + test_move_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffff02 + + moveq 2,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfa7,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x78134453,r3 + and.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + and.b [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/sim/cris/asm/andq.ms b/sim/testsuite/sim/cris/asm/andq.ms new file mode 100644 index 00000000000..e515b3e0e3a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/andq.ms @@ -0,0 +1,46 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + andq 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + andq -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + andq -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + andq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + andq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq -1,r3 + andq -32,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffe0 + + move.d 0x78134457,r3 + andq -14,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq 0,r3 + andq -14,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/andr.ms b/sim/testsuite/sim/cris/asm/andr.ms new file mode 100644 index 00000000000..f5d90e2d84b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/andr.ms @@ -0,0 +1,95 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r4 + move.d r4,r3 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + and.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + and.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 50124400 + + moveq -1,r3 + moveq 2,r4 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0002 + + moveq 2,r3 + moveq -1,r4 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xfffff,r3 + move.d 0xffff,r4 + and.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffff + + move.d 0xfedaffaf,r3 + move.d 0xff5f,r4 + and.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaff0f + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + and.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134400 + + moveq -1,r3 + moveq 2,r4 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff02 + + moveq 2,r3 + moveq -1,r4 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0x5a,r4 + move.d 0xfa7,r3 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f02 + + move.d 0x5432f789,r4 + move.d 0x78134453,r3 + and.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 78134401 + + moveq 0,r7 + and.b r7,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 78134400 + + quit diff --git a/sim/testsuite/sim/cris/asm/asm.exp b/sim/testsuite/sim/cris/asm/asm.exp new file mode 100644 index 00000000000..16fa6573a2a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/asm.exp @@ -0,0 +1,46 @@ +# Copyright (C) 2005 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +# Miscellaneous CRIS simulator testcases in assembly code. + +if [istarget cris*-*-*] { + global ASFLAGS_FOR_TARGET + # All machines we test and the corresponding assembler option. Needs + # update if we build the simulator for crisv0 crisv3 and crisv8 too. + + set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} + {"crisv32" "--march=v32"}} + + # We need to pass different assembler flags for each machine. + # Specifying it here rather than adding a specifier to each and every + # test-file is preferrable. + + foreach combo $combos { + set mach [lindex $combo 0] + set ASFLAGS_FOR_TARGET "[lindex $combo 1]" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $mach + } + } +} diff --git a/sim/testsuite/sim/cris/asm/asr.ms b/sim/testsuite/sim/cris/asm/asr.ms new file mode 100644 index 00000000000..d24ad4a8bfc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/asr.ms @@ -0,0 +1,228 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n1\nffffffff\nffffffff\n5a67f\nffffffff\nffffffff\nffffffff\nf699fc67\nffffffff\n1\nffffffff\nffffffff\n5a67f\nda67ffff\nda67ffff\nda67ffff\nda67fc67\nffffffff\nffffffff\n1\nffffffff\nffffffff\n5a670007\nda67f1ff\nda67f1ff\nda67f1ff\nda67f1e7\nffffffff\nffffffff\n1\nffffffff\nffffffff\nffffffff\n5a67f1ff\n5a67f1f9\n0\n5a670000\n + + .include "testutils.inc" + start + moveq -1,r3 + asrq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + asrq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + asrq 31,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + asrq 15,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + asrq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; f699fc67 + + moveq -1,r3 + moveq 0,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + asr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67ffff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67fc67 + + moveq -1,r3 + moveq 0,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67719f,r3 + moveq 12,r4 + asr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a670007 + + move.d 0xda67f19f,r3 + move.d 31,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 32,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 33,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1ff + + move.d 0xda67f19f,r3 + move.d 66,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67f1e7 + + moveq -1,r3 + moveq 0,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + asr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 15,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 7,r4 + asr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + asr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f1ff + + move.d 0x5a67f19f,r3 + moveq 4,r4 + asr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f1f9 + + move.d 0x5a67f19f,r3 + asrq 31,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5a67419f,r3 + moveq 16,r4 + asr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a670000 + + quit diff --git a/sim/testsuite/sim/cris/asm/ba.ms b/sim/testsuite/sim/cris/asm/ba.ms new file mode 100644 index 00000000000..12119621e64 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ba.ms @@ -0,0 +1,93 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: a\n + + .include "testutils.inc" + + .if ..asm.arch.cris.v32 + .set smalloffset,0 + .set largeoffset,0 + .else + .set smalloffset,2 + .set largeoffset,4 + .endif + + start + moveq 0,r3 + +; Short forward branch. + ba 0f + addq 1,r3 + fail + +; Max short forward branch. +1: + ba 2f + addq 1,r3 + fail + +; Short backward branch. +0: + ba 1b + addq 1,r3 + fail + + .space 254-2+smalloffset+1b-.,0 + moveq 0,r3 + +2: +; Transit branch (long). + ba 3f + addq 1,r3 + fail + + moveq 0,r3 +4: +; Long forward branch. + ba 5f + addq 1,r3 + fail + + .space 256-2-smalloffset+4b-.,0 + + moveq 0,r3 + +; Max short backward branch. +3: + ba 4b + addq 1,r3 + fail + +5: +; Max long forward branch. + ba 6f + addq 1,r3 + fail + + .space 32766+largeoffset-2+5b-.,0 + + moveq 0,r3 +6: +; Transit branch. + ba 7f + addq 1,r3 + fail + + moveq 0,r3 +9: + dumpr3 + quit + +; Transit branch. + moveq 0,r3 +7: + ba 8f + addq 1,r3 + fail + + .space 32768-largeoffset+9b-.,0 + +8: +; Max long backward branch. + ba 9b + addq 1,r3 + fail diff --git a/sim/testsuite/sim/cris/asm/bare1.ms b/sim/testsuite/sim/cris/asm/bare1.ms new file mode 100644 index 00000000000..6c7d0d2394a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bare1.ms @@ -0,0 +1,24 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# output: 0\n0\n4\n42\n +# sim: --cris-naked + +; Check that we don't get signs of an initialized environment +; when --cris-naked. + + .include "testutils.inc" + .text + .global _start +_start: + nop + nop +start2: + move.d $r10,$r3 + dumpr3 + move.d $sp,$r3 + dumpr3 + lapc start2,$r3 + dumpr3 + move.d 0x42,$r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/bare2.ms b/sim/testsuite/sim/cris/asm/bare2.ms new file mode 100644 index 00000000000..f30fd10e070 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bare2.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# output: 0\n0\n4\n42\n +# sim: --cris-naked --target binary --architecture crisv32 +# ld: --oformat binary + +; Check that we can run a naked binary with the same expected +; results as an ELF "executable". + + .include "bare1.ms" diff --git a/sim/testsuite/sim/cris/asm/bas.ms b/sim/testsuite/sim/cris/asm/bas.ms new file mode 100644 index 00000000000..084b5bfebca --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bas.ms @@ -0,0 +1,102 @@ +# mach: crisv32 +# output: 0\n0\n0\nfb349abc\n0\n12124243\n0\n0\neab5baad\n0\nefb37832\n + + .include "testutils.inc" + start +x: + setf zncv + bsr 0f + nop +0: + test_cc 1 1 1 1 + move srp,r3 + sub.d 0b,r3 + dumpr3 + + bas 1f,mof + moveq 0,r0 +6: + nop + quit + +2: + move srp,r3 + sub.d 3f,r3 + dumpr3 + move srp,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + basc 4f,mof + nop + .dword 0x12124243 +7: + nop + quit + +8: + move mof,r3 + sub.d 7f,r3 + dumpr3 + + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + jasc 9f,mof + nop + .dword 0xefb37832 +0: + quit + + quit +9: + move mof,r3 + sub.d 0b,r3 + dumpr3 + + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + + quit + +4: + move mof,r3 + sub.d 7b,r3 + dumpr3 + move mof,r4 + subq 4,r4 + move.d [r4],r3 + dumpr3 + basc 5f,bz + moveq 0,r3 + .dword 0x7634aeba + quit + + .space 32770,0 +1: + move mof,r3 + sub.d 6b,r3 + dumpr3 + + bsrc 2b + nop + .dword 0xfb349abc +3: + + quit + +5: + move mof,r3 + sub.d 7b,r3 + dumpr3 + move.d 8b,r6 + jasc r6,mof + nop + .dword 0xeab5baad +7: + quit diff --git a/sim/testsuite/sim/cris/asm/bccb.ms b/sim/testsuite/sim/cris/asm/bccb.ms new file mode 100644 index 00000000000..da5e41584a1 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bccb.ms @@ -0,0 +1,181 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1c\n + + .include "testutils.inc" + start + moveq 0,r3 + + clearf nzvc + setf nzv + bcc 0f + addq 1,r3 + fail + +0: + clearf nzvc + setf nzv + bcs dofail + addq 1,r3 + + clearf nzvc + setf ncv + bne 1f + addq 1,r3 + +dofail: + fail + +1: + clearf nzvc + setf ncv + beq dofail + addq 1,r3 + + clearf nzvc + setf ncz + bvc 2f + addq 1,r3 + fail + +2: + clearf nzvc + setf ncz + bvs dofail + addq 1,r3 + + clearf nzvc + setf vcz + bpl 3f + addq 1,r3 + fail + +3: + clearf nzvc + setf vcz + bmi dofail + addq 1,r3 + + clearf nzvc + setf nv + bls dofail + addq 1,r3 + + clearf nzvc + setf nv + bhi 4f + addq 1,r3 + fail + +4: + clearf nzvc + setf zc + bge 5f + addq 1,r3 + fail + +5: + clearf nzvc + setf zc + blt dofail + addq 1,r3 + + clearf nzvc + setf c + bgt 6f + addq 1,r3 + fail + +6: + clearf nzvc + setf c + ble dofail + addq 1,r3 + +;;;;;;;;;; + + setf nzvc + clearf nzv + bcc dofail + addq 1,r3 + + setf nzvc + clearf nzv + bcs 0f + addq 1,r3 + fail + +0: + setf nzvc + clearf ncv + bne dofail + addq 1,r3 + + setf nzvc + clearf ncv + beq 1f + addq 1,r3 + fail + +1: + setf nzvc + clearf ncz + bvc dofail + addq 1,r3 + + setf nzvc + clearf ncz + bvs 2f + addq 1,r3 + fail + +2: + setf nzvc + clearf vcz + bpl dofail + addq 1,r3 + + setf nzvc + clearf vcz + bmi 3f + addq 1,r3 + fail + +3: + setf nzvc + clearf nv + bls 4f + addq 1,r3 + fail + +4: + setf nzvc + clearf nv + bhi dofail + addq 1,r3 + + setf zvc + clearf nzc + bge dofail + addq 1,r3 + + setf nzc + clearf vzc + blt 5f + addq 1,r3 + fail + +5: + setf nzvc + clearf c + bgt dofail + addq 1,r3 + + setf nzvc + clearf c + ble 6f + addq 1,r3 + fail + +6: + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/bdapc.ms b/sim/testsuite/sim/cris/asm/bdapc.ms new file mode 100644 index 00000000000..cfedd8be264 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bdapc.ms @@ -0,0 +1,57 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\n88ccee19\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0xb232765a + + start + moveq -1,r0 + moveq -1,r2 + move.d x-32768,r5 + move.d [r5+32769],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + bdap.w -1,r5 + move.d [r0],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + bdap.d 4,r5 + move.d [r2+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ee19ccff + + bdap.b 2,r2 + move.d [r3],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 88ccee19 + + bdap.b 3,r5 + movu.w [r4+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff22 + + bdap.b -4,r4 + move.d [r6+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + bdap.w 2,r6 + move.d [r3],r9 + test_move_cc 1 0 0 0 + dumpr3 ; ff224455 + + add.d 76789885,r5 + bdap.d -76789887,r5 + move.d [r3],r9 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/bdapm.ms b/sim/testsuite/sim/cris/asm/bdapm.ms new file mode 100644 index 00000000000..26bc4ad3aac --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bdapm.ms @@ -0,0 +1,56 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 +y: + .dword 32769 + .word -1 + .dword 5 + .byte 3,-4 + .word 2 + .dword -76789887 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d y,r13 + bdap.d [r13+],r5 + move.d [r3],r9 + test_move_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32770,r5 + bdap.w [r13+],r5 + move.d [r9+],r3 + dumpr3 ; 4455aa77 + + bdap.d [r13],r9 + move.d [r3],r7 + addq 4,r13 + dumpr3 ; ee19ccff + + bdap.b [r13+],r5 + movu.w [r7+],r3 + dumpr3 ; ff22 + + bdap.b [r13],r7 + move.d [r7+],r3 + addq 1,r13 + dumpr3 ; 4455aa77 + + bdap.w [r13],r7 + move.d [r3],r3 + addq 2,r13 + dumpr3 ; ff224455 + + add.d 76789885,r5 + bdap.d [r13+],r5 + move.d [r3],r9 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/bdapq.ms b/sim/testsuite/sim/cris/asm/bdapq.ms new file mode 100644 index 00000000000..a0ba406353f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bdapq.ms @@ -0,0 +1,29 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n0\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0 + start + moveq -1,r0 + move.d x+4,r5 + move.d [r5+0],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ccff2244 + move.d [r5=r5+4],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 88ccee19 + move.d [r5=r5-8],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + movu.w [r5+7],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 19cc + move.d [r5+12],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + quit diff --git a/sim/testsuite/sim/cris/asm/bdapqpc.ms b/sim/testsuite/sim/cris/asm/bdapqpc.ms new file mode 100644 index 00000000000..f2209efec28 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/bdapqpc.ms @@ -0,0 +1,30 @@ +# mach: crisv3 crisv8 crisv10 +# output: aaeebb11\nde378218\n + +# Test that the special case "X [pc+I],Y" works, where I byte-sized. + + .include "testutils.inc" + start +x: +; FIXME: Gas bugs are making this a bit harder than necessary. +; move.d [pc+y-(.+2)],r3 + move.d [pc+8],r3 +yy: + jump zz + +y: + .dword 0xaaeebb11 +y2: + .dword 0xde378218 + +zz: + dumpr3 + jump z + quit + +; Check a negative offset. + .space 50 +z: + move.d [pc+y2-(.+2)],r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/biap.ms b/sim/testsuite/sim/cris/asm/biap.ms new file mode 100644 index 00000000000..a51a9189ac5 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/biap.ms @@ -0,0 +1,56 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + moveq -1,r0 + move.d x-32768,r5 + move.d 32769,r6 + move.d [r5+r6.b],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + addu.w 32771,r5 + moveq -1,r8 + move.d [r11=r5+r8.w],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + moveq 5,r10 + move.d [r11+r10.b],r3 + test_cc 1 0 0 0 + dumpr3 ; ee19ccff + + subq 1,r5 + move.d r5,r8 + subq 1,r8 + moveq 1,r9 + movu.w [r12=r8+r9.d],r3 + test_cc 0 0 0 0 + dumpr3 ; ff22 + + moveq -2,r11 + move.d [r13=r12+r11.w],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + subq 18,r13 + moveq 5,r9 + move.d [r13+r9.d],r3 + test_cc 1 0 0 0 + dumpr3 ; ff224455 + + move.d r5,r7 + add.d 76789886,r7 + move.d -76789888/4,r12 + move.d [r7+r12.d],r3 + test_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/boundc.ms b/sim/testsuite/sim/cris/asm/boundc.ms new file mode 100644 index 00000000000..0b2be137489 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/boundc.ms @@ -0,0 +1,101 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\nff\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + bound.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.d 0xffffffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.d 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + bound.d 0xffffffff,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + bound.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + bound.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq 2,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + bound.w 0xffff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x78134452,r3 + bound.w 0xf789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + bound.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xff,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + bound.b 0xff,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x78134452,r3 + bound.b 0x89,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + bound.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + bound.b -1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + quit diff --git a/sim/testsuite/sim/cris/asm/boundm.ms b/sim/testsuite/sim/cris/asm/boundm.ms new file mode 100644 index 00000000000..91019dd4fdb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/boundm.ms @@ -0,0 +1,105 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\n + + .include "testutils.inc" + .data +x: + .dword 2,-1,0xffff,-1,0x5432f789 + .word 2,0xffff,0xf789 + .byte 2,0xff,0x89,0 + + start + move.d x,r5 + + moveq -1,r3 + moveq 2,r4 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.d [r5],r3 + test_move_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + bound.d [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + bound.d [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq 2,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + bound.w [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x78134452,r3 + bound.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xff,r3 + bound.b [r5],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x78134452,r3 + bound.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + bound.b [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/boundmv32.ms b/sim/testsuite/sim/cris/asm/boundmv32.ms new file mode 100644 index 00000000000..4aad1ef58ef --- /dev/null +++ b/sim/testsuite/sim/cris/asm/boundmv32.ms @@ -0,0 +1,15 @@ +# mach: crisv32 +# xerror: +# output: program stopped with signal 4.\n + .include "testutils.inc" + +; Check that bound with a memory operand is invalid. + start + move.d 0f,r5 + move.d r5,r3 + .byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it. + pass + +0: + .dword 0b + diff --git a/sim/testsuite/sim/cris/asm/boundr.ms b/sim/testsuite/sim/cris/asm/boundr.ms new file mode 100644 index 00000000000..bc6a90d971e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/boundr.ms @@ -0,0 +1,125 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\nffff\nffffffff\n5432f789\n2\n2\nffff\nffff\nffff\nf789\n2\n2\nff\nff\n89\nfeda4953\nfeda4962\n0\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r4 + move.d r4,r3 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5432f789 + + moveq -1,r3 + moveq 2,r4 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq -1,r3 + bound.w r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r4 + move.d r4,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r4 + move.d r4,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; f789 + + moveq -1,r3 + moveq 2,r4 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + moveq 2,r3 + moveq -1,r4 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r4 + move.d r4,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r4 + move.d r4,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + bound.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 89 + + move.d 0xfeda4956,r3 + move.d 0xfeda4953,r4 + bound.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feda4953 + + move.d 0xfeda4962,r3 + move.d 0xfeda4963,r4 + bound.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feda4962 + + move.d 0xfeda4956,r3 + move.d 0,r4 + bound.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xfeda4956,r4 + move.d 0,r3 + bound.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/break.ms b/sim/testsuite/sim/cris/asm/break.ms new file mode 100644 index 00000000000..c1a7a960662 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/break.ms @@ -0,0 +1,15 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# sim: --trace-core=on +# ld: --section-start=.text=0 +# output: read-2 exec:0x00000002 -> 0x05b0\nread-2 exec:0x00000004 -> 0xe93f\n + +; First test: Must exit gracefully. + + .include "testutils.inc" + +; This first insn isn't executed (it's a filler); it would fail +; ungracefully if executed. + + startnostack + setf + quit diff --git a/sim/testsuite/sim/cris/asm/btst.ms b/sim/testsuite/sim/cris/asm/btst.ms new file mode 100644 index 00000000000..b63e8f2cd26 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/btst.ms @@ -0,0 +1,87 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1111\n + + .include "testutils.inc" + start + clearf nzvc + moveq -1,r3 + .if ..asm.arch.cris.v32 + .else + setf vc + .endif + btstq 0,r3 + test_cc 1 0 0 0 + + moveq 2,r3 + btstq 1,r3 + test_cc 1 0 0 0 + + moveq 4,r3 + btstq 1,r3 + test_cc 0 1 0 0 + + moveq -1,r3 + btstq 31,r3 + test_cc 1 0 0 0 + + move.d 0x5a67f19f,r3 + btstq 12,r3 + test_cc 1 0 0 0 + + move.d 0xda67f19f,r3 + move.d 29,r4 + btst r4,r3 + test_cc 0 0 0 0 + + move.d 0xda67f19f,r3 + move.d 32,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0xda67f191,r3 + move.d 33,r4 + btst r4,r3 + test_cc 0 0 0 0 + + moveq -1,r3 + moveq 0,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq 2,r3 + moveq 1,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq -1,r3 + moveq 31,r4 + btst r4,r3 + test_cc 1 0 0 0 + + moveq 4,r3 + btstq 1,r3 + test_cc 0 1 0 0 + + moveq -1,r3 + moveq 15,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + btst r4,r3 + test_cc 1 0 0 0 + + move.d 0x5a678000,r3 + moveq 11,r4 + btst r4,r3 + test_cc 0 1 0 0 + + move.d 0x5a67f19f,r3 + btst r3,r3 + test_cc 0 0 0 0 + + move.d 0x1111,r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/ccr-v10.ms b/sim/testsuite/sim/cris/asm/ccr-v10.ms new file mode 100644 index 00000000000..39602f01bd0 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ccr-v10.ms @@ -0,0 +1,79 @@ +# mach: crisv10 +# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n + +; Check that flag settings affect ccr and dccr and vice versa. + + .include "testutils.inc" + start + clear.d r3 + setf mbixnzvc + move ccr,r3 + dumpr3 + + clear.d r3 + setf mbixnzvc + move dccr,r3 + dumpr3 + + clear.d r3 + clearf mbixnzvc + move ccr,r3 + dumpr3 + + clear.d r3 + clearf mbixnzvc + move dccr,r3 + dumpr3 + + .macro testfr BIT REG + clear.d r3 + clearf mbixnzvc + setf \BIT + move \REG,r3 + dumpr3 + .endm + + testfr m ccr + testfr b ccr + testfr i ccr + testfr x ccr + testfr n ccr + testfr z ccr + testfr v ccr + testfr c ccr + + testfr m dccr + testfr b dccr + testfr i dccr + testfr x dccr + testfr n dccr + testfr z dccr + testfr v dccr + testfr c dccr + +; Check only the nzvc bits; do the other bits in special tests as they're +; implemented. + .macro test_get_cc N Z V C + clearf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr + test_cc \N \Z \V \C + setf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr + test_cc \N \Z \V \C + move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 + setf znvc + move r4,ccr + test_cc \N \Z \V \C + clearf znvc + move r4,dccr + test_cc \N \Z \V \C + .endm + + test_get_cc 1 0 0 0 + test_get_cc 0 1 0 0 + test_get_cc 0 0 1 0 + test_get_cc 0 0 0 1 + + move.d 0x42,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/ccs-v32.ms b/sim/testsuite/sim/cris/asm/ccs-v32.ms new file mode 100644 index 00000000000..8dc60262fc2 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ccs-v32.ms @@ -0,0 +1,73 @@ +# mach: crisv32 +# output: bf\n0\n80\n20\n10\n8\n4\n2\n1\n40\nfade040\n3ade0040\nfade040\n42\n + +; Check flag settings. + + .include "testutils.inc" + start + clear.d r3 + setf pixnzvc ; Setting U(ser mode) would restrict tests of other flags. + move ccs,r3 + dumpr3 + + clear.d r3 + clearf puixnzvc + move ccs,r3 + dumpr3 + + .macro testf BIT + clear.d r3 + clearf puixnzvc + setf \BIT + move ccs,r3 + dumpr3 + .endm + + testf p + testf i + testf x + testf n + testf z + testf v + testf c + testf u ; Can't test i-flag or clear u after this point. + + .macro test_get_cc N Z V C + clearf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs + test_cc \N \Z \V \C + setf znvc + move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs + test_cc \N \Z \V \C + move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 + setf znvc + move r4,ccs + test_cc \N \Z \V \C + clearf znvc + move r4,ccs + test_cc \N \Z \V \C + .endm + + test_get_cc 1 0 0 0 + test_get_cc 0 1 0 0 + test_get_cc 0 0 1 0 + test_get_cc 0 0 0 1 + +; Test that the U bit sticks. + move 0x0fade000,ccs + move ccs,r3 + dumpr3 + +; Check that the M and Q bits can't be set in user mode. + move 0xfade0000,ccs + move ccs,r3 + dumpr3 + + move 0x0fade000,ccs + move ccs,r3 + dumpr3 + + move.d 0x42,r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/clearfv10.ms b/sim/testsuite/sim/cris/asm/clearfv10.ms new file mode 100644 index 00000000000..d910842942f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/clearfv10.ms @@ -0,0 +1,12 @@ +# mach: crisv10 +# output: ef\n + +; Check that "clearf x" doesn't trivially fail. + + .include "testutils.inc" + start + setf mbixnzvc + clearf x ; Actually, x would be cleared by almost-all other insns. + move dccr,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/clearfv32.ms b/sim/testsuite/sim/cris/asm/clearfv32.ms new file mode 100644 index 00000000000..b1dd3dec517 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/clearfv32.ms @@ -0,0 +1,12 @@ +# mach: crisv32 +# output: ef\n + +; Check that "clearf x" doesn't trivially fail. + + .include "testutils.inc" + start + setf puixnzvc + clearf x ; Actually, x would be cleared by almost-all other insns. + move ccs,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/clrjmp1.ms b/sim/testsuite/sim/cris/asm/clrjmp1.ms new file mode 100644 index 00000000000..1a76e7fc8bb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/clrjmp1.ms @@ -0,0 +1,36 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\n + +; A bug resulting in a non-effectual clear.b discovered running the GCC +; testsuite; jump actually wrote to p0. + + .include "testutils.inc" + + start + jump 1f + nop + .p2align 8 +1: + move.d y,r4 + + .if 0 == ..asm.arch.cris.v32 +; There was a bug causing this insn to set special register p0 +; (byte-clear) to 8 (low 8 bits of location after insn). + jump [r4+] + .endif + +1: + move.d 0f,r4 + +; The corresponding bug would cause this insn too, to set p0. + jump r4 + nop + quit +0: + moveq -1,r3 + clear.b r3 + dumpr3 + quit + +y: + .dword 1b diff --git a/sim/testsuite/sim/cris/asm/cmpc.ms b/sim/testsuite/sim/cris/asm/cmpc.ms new file mode 100644 index 00000000000..8600f5f7919 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpc.ms @@ -0,0 +1,86 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649282\n + + .include "testutils.inc" + start + moveq -1,r3 + cmp.d -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.d 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.d -0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmp.d 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmp.d -0x5432f789,r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.w -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.w 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + cmp.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + cmp.w 0x877,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.b -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.b 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r3 + cmp.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + cmp.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d 0x78134452,r3 + cmp.b 0x77,r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649282,r3 + cmp.b 0x82,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649282 + + quit diff --git a/sim/testsuite/sim/cris/asm/cmpm.ms b/sim/testsuite/sim/cris/asm/cmpm.ms new file mode 100644 index 00000000000..753f2d36f06 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n + + .include "testutils.inc" + .data +x: + .dword -2,1,-0xffff,1,-0x5432f789 + .word -2,1,1,0x877 + .byte -2,1,0x77 + .byte 0x22 + + start + moveq -1,r3 + move.d x,r5 + cmp.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.d [r5],r3 + test_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmp.d [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmp.d [r5+],r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmp.w [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + cmp.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + cmp.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + cmp.b [r5],r3 + test_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffffff + + moveq 2,r3 + cmp.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xff,r3 + cmp.b [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d 0xfeda49ff,r3 + cmp.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d 0x78134452,r3 + cmp.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649222,r3 + cmp.b [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 85649222 + + quit diff --git a/sim/testsuite/sim/cris/asm/cmpq.ms b/sim/testsuite/sim/cris/asm/cmpq.ms new file mode 100644 index 00000000000..7e40be4907d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpq.ms @@ -0,0 +1,75 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1\n1f\n1f\nffffffe1\nffffffe1\nffffffe0\n0\n0\nffffffff\nffffffff\n10000\n100\n5678900\n + + .include "testutils.inc" + start + moveq 1,r3 + cmpq 1,r3 + test_cc 0 1 0 0 + dumpr3 ; 1 + + cmpq -1,r3 + test_cc 0 0 0 1 + dumpr3 ; 1 + + cmpq 31,r3 + test_cc 1 0 0 1 + dumpr3 ; 1 + + moveq 31,r3 + cmpq 31,r3 + test_cc 0 1 0 0 + dumpr3 ; 1f + + cmpq -31,r3 + test_cc 0 0 0 1 + dumpr3 ; 1f + + movs.b -31,r3 + cmpq -31,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffe1 + + cmpq -32,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffe1 + + movs.b -32,r3 + cmpq -32,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffe0 + + moveq 0,r3 + cmpq 1,r3 + test_cc 1 0 0 1 + dumpr3 ; 0 + + cmpq -32,r3 + test_cc 0 0 0 1 + dumpr3 ; 0 + + moveq -1,r3 + cmpq 1,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + cmpq -1,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x10000,r3 + cmpq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 10000 + + move.d 0x100,r3 + cmpq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 100 + + move.d 0x5678900,r3 + cmpq 7,r3 + test_cc 0 0 0 0 + dumpr3 ; 5678900 + + quit diff --git a/sim/testsuite/sim/cris/asm/cmpr.ms b/sim/testsuite/sim/cris/asm/cmpr.ms new file mode 100644 index 00000000000..6730a000c49 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpr.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq -2,r4 + cmp.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + move.d -0xffff,r4 + cmp.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq 1,r4 + moveq -1,r3 + cmp.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.d r4,r3 + test_cc 1 0 1 1 + dumpr3 ; 78134452 + + moveq -1,r3 + moveq -2,r4 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d 0xffff,r3 + move.d -0xffff,r4 + cmp.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffff + + move.d 0xfedaffff,r3 + move.d -0xfedaffff,r4 + cmp.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + moveq -1,r3 + moveq -2,r4 + cmp.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + cmp.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2 + + move.d -0xff,r4 + move.d 0xff,r3 + cmp.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ff + + move.d -0xfeda49ff,r4 + move.d 0xfeda49ff,r3 + cmp.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49ff + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + cmp.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; 78134452 + + move.d 0x85649222,r3 + move.d 0x77445622,r4 + cmp.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649222 + + quit diff --git a/sim/testsuite/sim/cris/asm/cmpxc.ms b/sim/testsuite/sim/cris/asm/cmpxc.ms new file mode 100644 index 00000000000..d9acd8fcb4b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpxc.ms @@ -0,0 +1,92 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n + + .include "testutils.inc" + start + moveq 2,r3 + cmps.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmps.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmpu.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + move.d 0xffffffff,r4 + cmpu.w -1,r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmpu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmpu.w -1,r3 + test_cc 0 1 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmps.b 0xff,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w 0xff,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w 0xffff,r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmpu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmpu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x4452,r3 + cmps.w 0x8002,r3 + test_cc 0 0 0 1 + dumpr3 ; 4452 + + move.d 0x80000032,r3 + cmpu.w 0x764,r3 + test_cc 0 0 1 0 + dumpr3 ; 80000032 + + quit diff --git a/sim/testsuite/sim/cris/asm/cmpxm.ms b/sim/testsuite/sim/cris/asm/cmpxm.ms new file mode 100644 index 00000000000..6a87ab044c8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/cmpxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .word 0x8002 + .word 0x764 + + start + moveq 2,r3 + move.d x,r5 + cmps.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + subq 3,r5 + cmpu.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 2 + + moveq 2,r3 + cmpu.w [r5+],r3 + test_cc 1 0 0 1 + subq 3,r5 + dumpr3 ; 2 + + move.d 0xffff,r3 + cmpu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmpu.w [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + move.d 0xffff,r3 + cmps.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; ffff + + moveq -1,r3 + cmps.b [r5],r3 + test_cc 0 1 0 0 + addq 3,r5 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + cmps.w [r5+],r3 + test_cc 0 1 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + cmpu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmpu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78134452 + + move.d 0x78134452,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134452 + + move.d 0x4452,r3 + cmps.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 4452 + + move.d 0x80000032,r3 + cmpu.w [r5+],r3 + test_cc 0 0 1 0 + dumpr3 ; 80000032 + + quit diff --git a/sim/testsuite/sim/cris/asm/dflags.ms b/sim/testsuite/sim/cris/asm/dflags.ms new file mode 100644 index 00000000000..273501425b8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/dflags.ms @@ -0,0 +1,62 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 31\n + +; Check that flag settings in the delay slot for a conditional branch do +; not affect the branch. + + .include "testutils.inc" + + start + moveq 1,r3 + moveq 0,r4 + +; 8-bit branches. + + move.d r4,r4 + bne 0f + move.d r3,r3 + bne 1f + move.d r4,r4 + nop +0: + quit + +1: + move.d r3,r3 + beq 0b + move.d r4,r4 + beq 4f + move.d r3,r3 + nop + quit +4: + jump 2f + nop + .space 1000 + +; 16-bit branches + +2: + move.d r4,r4 + bne 0b + move.d r3,r3 + bne 3f + move.d r4,r4 + nop + quit + .space 1000 + +3: + move.d r3,r3 + beq 0b + move.d r4,r4 + beq 4f + move.d r3,r3 + nop + quit + .space 1000 + +4: + move.d 0x31,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/dip.ms b/sim/testsuite/sim/cris/asm/dip.ms new file mode 100644 index 00000000000..ff79f22239c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/dip.ms @@ -0,0 +1,41 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 4455aa77\nee19ccff\nb232765a\nff22\n5a88ccee\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + .dword 0xb232765a +y: + .dword x+12 + .dword x+5 + .dword x+9 + + start + moveq -1,r0 + moveq -1,r2 + move.d [x+1],r3 + test_cc 0 0 0 0 + dumpr3 ; 4455aa77 + + move.d [x+6],r3 + test_cc 1 0 0 0 + dumpr3 ; ee19ccff + + move.d y,r8 + move.d [[r8+]],r3 + test_cc 1 0 0 0 + dumpr3 ; b232765a + + movu.w [[r8]],r3 + test_cc 0 0 0 0 + dumpr3 ; ff22 + addq 4,r8 + + move.d [[r8]],r3 + test_cc 0 0 0 0 + dumpr3 ; 5a88ccee + + quit diff --git a/sim/testsuite/sim/cris/asm/dstep.ms b/sim/testsuite/sim/cris/asm/dstep.ms new file mode 100644 index 00000000000..25beda0fc89 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/dstep.ms @@ -0,0 +1,42 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: fffffffc\n4\nffff\nfffffffe\n9bf3911b\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + dstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffc + + moveq 2,r3 + moveq -1,r4 + dstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + move.d 0xffff,r4 + move.d r4,r3 + dstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + dstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + dstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 9bf3911b + + move.d 0xffff,r3 + move.d 0x1fffe,r4 + dstep r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/fidxd.ms b/sim/testsuite/sim/cris/asm/fidxd.ms new file mode 100644 index 00000000000..447e397e178 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/fidxd.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + fidxd [r3] + + quit diff --git a/sim/testsuite/sim/cris/asm/fidxi.ms b/sim/testsuite/sim/cris/asm/fidxi.ms new file mode 100644 index 00000000000..fdee4483d54 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/fidxi.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + fidxi [r5] + + quit diff --git a/sim/testsuite/sim/cris/asm/ftagd.ms b/sim/testsuite/sim/cris/asm/ftagd.ms new file mode 100644 index 00000000000..87c7f130adf --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ftagd.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + ftagd [r11] + + quit diff --git a/sim/testsuite/sim/cris/asm/ftagi.ms b/sim/testsuite/sim/cris/asm/ftagi.ms new file mode 100644 index 00000000000..506847648db --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ftagi.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + ftagi [r8] + + quit diff --git a/sim/testsuite/sim/cris/asm/halt.ms b/sim/testsuite/sim/cris/asm/halt.ms new file mode 100644 index 00000000000..368c367479b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/halt.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: HALT isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + halt + + quit diff --git a/sim/testsuite/sim/cris/asm/io1.ms b/sim/testsuite/sim/cris/asm/io1.ms new file mode 100644 index 00000000000..a8335a8097b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io1.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# sim: --cris-900000xx --memory-region 0x90000000,0x10 +# xerror: +# output: Seeing --cris-900000xx with memory defined there\n + +; Check that I/O region overlap is detected. + + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/io2.ms b/sim/testsuite/sim/cris/asm/io2.ms new file mode 100644 index 00000000000..f6341d3739d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io2.ms @@ -0,0 +1,18 @@ +# mach: crisv32 +# sim: --cris-900000xx +# xerror: +# output: b1e\n + +; Check correct "fail" exit. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io3.ms b/sim/testsuite/sim/cris/asm/io3.ms new file mode 100644 index 00000000000..664dc61d267 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io3.ms @@ -0,0 +1,17 @@ +# mach: crisv32 +# sim: --cris-900000xx +# output: ce11d0c\n + +; Check correct "pass" exit. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io4.ms b/sim/testsuite/sim/cris/asm/io4.ms new file mode 100644 index 00000000000..f925dbd3448 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io4.ms @@ -0,0 +1,18 @@ +# mach: crisv32 +# xerror: +# output: b1e\n + +; Check correct "fail" exit. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + moveq 1,$r9 + moveq 2,$r10 + break 13 + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io5.ms b/sim/testsuite/sim/cris/asm/io5.ms new file mode 100644 index 00000000000..178a4d7f857 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io5.ms @@ -0,0 +1,17 @@ +# mach: crisv32 +# output: ce11d0c\n + +; Check correct "pass" exit. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + moveq 1,$r9 + moveq 0,$r10 + break 13 + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io6.ms b/sim/testsuite/sim/cris/asm/io6.ms new file mode 100644 index 00000000000..6f3c25d04b8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io6.ms @@ -0,0 +1,22 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# sim: --cris-900000xx +# xerror: +# output: b1e\n +# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n +# output: program stopped with signal 11.\n + +; Check that invalid access to the simulator area is recognized. +; "FAIL" area. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + clear.d [$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io7.ms b/sim/testsuite/sim/cris/asm/io7.ms new file mode 100644 index 00000000000..8c8b46122d0 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io7.ms @@ -0,0 +1,22 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# sim: --cris-900000xx +# xerror: +# output: ce11d0c\n +# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n +# output: program stopped with signal 11.\n + +; Check that invalid access to the simulator area is recognized. +; "PASS" area. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + clear.d [$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io8.ms b/sim/testsuite/sim/cris/asm/io8.ms new file mode 100644 index 00000000000..0ba9287b881 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io8.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# xerror: +# output: b1e\n +# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n +# output: program stopped with signal 11.\n + +; Check invalid access valid with --cris-900000xx. +; "FAIL" area. + + .include "testutils.inc" + start + move.d 0xb1e,$r3 + dumpr3 + move.d 0x90000008,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/io9.ms b/sim/testsuite/sim/cris/asm/io9.ms new file mode 100644 index 00000000000..afcb5913ac6 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/io9.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# ld: --section-start=.text=0 +# xerror: +# output: ce11d0c\n +# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n +# output: program stopped with signal 11.\n + +; Check invalid access valid with --cris-900000xx. +; "PASS" area. + + .include "testutils.inc" + start + move.d 0x0ce11d0c,$r3 + dumpr3 + move.d 0x90000004,$acr + move.d $acr,[$acr] + move.d 0xbadc0de,$r3 + dumpr3 +0: + ba 0b + nop diff --git a/sim/testsuite/sim/cris/asm/jsr.ms b/sim/testsuite/sim/cris/asm/jsr.ms new file mode 100644 index 00000000000..95dd7c5f6cb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/jsr.ms @@ -0,0 +1,85 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 0\n0\n0\n0\n0\n0\n + +# Test that jsr Rn and jsr [PC+] work. + + .include "testutils.inc" + start +x: + move.d 0f,r6 + setf nzvc + jsr r6 + .if ..asm.arch.cris.v32 + nop + .endif +0: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 0b,r3 + dumpr3 + + move.d 1f,r0 + setf nzvc + jsr r0 + .if ..asm.arch.cris.v32 + moveq 0,r0 + .endif +6: + nop + quit + +2: + test_move_cc 0 0 0 0 + move srp,r3 + sub.d 3f,r3 + dumpr3 + jsr 4f + .if ..asm.arch.cris.v32 + nop + .endif +7: + nop + quit + +8: + move srp,r3 + sub.d 7b,r3 + dumpr3 + quit + +4: + move srp,r3 + sub.d 7b,r3 + dumpr3 + move.d 5f,r3 + jump r3 + .if ..asm.arch.cris.v32 + moveq 0,r3 + .endif + quit + + .space 32770,0 +1: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 6b,r3 + dumpr3 + + clearf cznv + jsr 2b + .if ..asm.arch.cris.v32 + nop + .endif +3: + + quit + +5: + move srp,r3 + sub.d 7b,r3 + dumpr3 + jump 8b + .if ..asm.arch.cris.v32 + nop + .endif + quit diff --git a/sim/testsuite/sim/cris/asm/jsrmv10.ms b/sim/testsuite/sim/cris/asm/jsrmv10.ms new file mode 100644 index 00000000000..fa9af060cf1 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/jsrmv10.ms @@ -0,0 +1,40 @@ +# mach: crisv3 crisv8 crisv10 +# output: 23\n + +# Test that jsr [] records the correct return-address. + + .include "testutils.inc" + start +x: + moveq 0,r3 + jsr [z] + addq 1,r3 + nop + nop + nop + nop + nop + move.d w,r2 + jsr [r2] + addq 1,r3 + nop + nop + nop + nop + nop + dumpr3 ; 23 + quit +y: + ret + addq 1,r3 + quit + +v: + ret + addq 32,r3 + quit + +z: + .dword y +w: + .dword v diff --git a/sim/testsuite/sim/cris/asm/jumpmp.ms b/sim/testsuite/sim/cris/asm/jumpmp.ms new file mode 100644 index 00000000000..dd21e9c6b38 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/jumpmp.ms @@ -0,0 +1,21 @@ +# mach: crisv3 crisv8 crisv10 +# output: bed0bed1\n + +# Test that jump indirect clears the "prefixed" +# bit. + + .include "testutils.inc" + .data +w: + .dword x1 +y: + .dword 0xbed0bed1 + + start +x: + move.d y,r3 + jump [w] +x1: + move.d [r3],r3 + dumpr3 ; bed0bed1 + quit diff --git a/sim/testsuite/sim/cris/asm/jumppv32.ms b/sim/testsuite/sim/cris/asm/jumppv32.ms new file mode 100644 index 00000000000..c37f42d323a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/jumppv32.ms @@ -0,0 +1,28 @@ +# mach: crisv32 +# output: 2222\n + +# Test that jump Pd works. + + .include "testutils.inc" + start +x: + setf zvnc + move 0f,srp + test_cc 1 1 1 1 + jump srp + nop + quit + +0: + test_cc 1 1 1 1 + move 1f,mof + jump mof + nop + quit + + .space 32768,0 + quit +1: + move.d 0x2222,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/lapc.ms b/sim/testsuite/sim/cris/asm/lapc.ms new file mode 100644 index 00000000000..bacd88126ed --- /dev/null +++ b/sim/testsuite/sim/cris/asm/lapc.ms @@ -0,0 +1,78 @@ +# mach: crisv32 +# output: 0\n0\nfffffffa\nfffffffe\nffffffda\n1e\n1e\n0\n + + .include "testutils.inc" + +; To accommodate dumpr3 with more than one instruction, keep it +; out of lapc operand ranges and difference calculations. + + start + lapc.d 0f,r3 +0: + sub.d .,r3 + dumpr3 ; 0 + + lapcq 0f,r3 +0: + sub.d .,r3 + dumpr3 ; 0 + + lapc.d .,r3 + sub.d .,r3 + dumpr3 ; fffffffa + + lapcq .,r3 + sub.d .,r3 + dumpr3 ; fffffffe + +0: + .rept 16 + nop + .endr + lapc.d 0b,r3 + sub.d .,r3 + dumpr3 ; ffffffda + + setf zcvn + lapc.d 0f,r3 + test_cc 1 1 1 1 + sub.d .,r3 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop +0: + dumpr3 ; 1e +0: + lapcq 0f,r3 + sub.d 0b,r3 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop +0: + dumpr3 ; 1e + clearf cn + setf zv +1: + lapcq .,r3 + test_cc 0 1 1 0 + sub.d 1b,r3 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/lsl.ms b/sim/testsuite/sim/cris/asm/lsl.ms new file mode 100644 index 00000000000..a2658b84045 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/lsl.ms @@ -0,0 +1,217 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n4\n80000000\nffff8000\n7f19f000\n80000000\n0\n0\n699fc67c\nffffffff\n4\n80000000\nffff8000\n7f19f000\nda670000\nda670000\nda670000\nda67c67c\nffffffff\nfffafffe\n4\nffff0000\nffff8000\n5a67f000\nda67f100\nda67f100\nda67f100\nda67f17c\nfff3faff\nfff3fafe\n4\nffffff00\nffffff00\nffffff80\n5a67f100\n5a67f1f0\n + + .include "testutils.inc" + start + moveq -1,r3 + lslq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + lslq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + lslq 31,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + moveq -1,r3 + lslq 15,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + lslq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7f19f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 699fc67c + + moveq -1,r3 + moveq 0,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + moveq -1,r3 + moveq 15,r4 + lsl.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7f19f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; da67c67c + + moveq -1,r3 + moveq 0,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0xfffaffff,r3 + moveq 1,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffafffe + + moveq 2,r3 + moveq 1,r4 + lsl.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffff0000 + + moveq -1,r3 + moveq 15,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff8000 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f000 + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsl.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da67f17c + + move.d 0xfff3faff,r3 + moveq 0,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fff3faff + + move.d 0xfff3faff,r3 + moveq 1,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fff3fafe + + moveq 2,r3 + moveq 1,r4 + lsl.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4 + + moveq -1,r3 + moveq 31,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 15,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 7,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffff80 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsl.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a67f100 + + move.d 0x5a67f19f,r3 + moveq 4,r4 + lsl.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 5a67f1f0 + + quit diff --git a/sim/testsuite/sim/cris/asm/lsr.ms b/sim/testsuite/sim/cris/asm/lsr.ms new file mode 100644 index 00000000000..e4991c6809b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/lsr.ms @@ -0,0 +1,217 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\n1\n1\n1ffff\n5a67f\n1\n0\n0\n3699fc67\nffffffff\n1\n1\n1ffff\n5a67f\nda670000\nda670000\nda670000\nda673c67\nffffffff\nffff7fff\n1\nffff0000\nffff0001\n5a67000f\nda67f100\nda67f100\nda67f100\nda67f127\nffffffff\nffffff7f\n1\nffffff00\nffffff00\nffffff01\n5a67f100\n5a67f109\n + + .include "testutils.inc" + start + moveq -1,r3 + lsrq 0,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + lsrq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + lsrq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + lsrq 15,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ffff + + move.d 0x5a67f19f,r3 + lsrq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.d r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3699fc67 + + moveq -1,r3 + moveq 0,r4 + lsr.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq 1,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 15,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ffff + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.w r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da670000 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da673c67 + + moveq -1,r3 + moveq 0,r4 + lsr.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff7fff + + moveq 2,r3 + moveq 1,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0000 + + moveq -1,r3 + moveq 15,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0001 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67000f + + move.d 0xda67f19f,r3 + move.d 31,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 32,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 33,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; da67f100 + + move.d 0xda67f19f,r3 + move.d 66,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; da67f127 + + moveq -1,r3 + moveq 0,r4 + lsr.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 1,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff7f + + moveq 2,r3 + moveq 1,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + moveq -1,r3 + moveq 31,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 15,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + moveq 7,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff01 + + move.d 0x5a67f19f,r3 + moveq 12,r4 + lsr.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 5a67f100 + + move.d 0x5a67f19f,r3 + moveq 4,r4 + lsr.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 5a67f109 + + quit diff --git a/sim/testsuite/sim/cris/asm/lz.ms b/sim/testsuite/sim/cris/asm/lz.ms new file mode 100644 index 00000000000..8a4bb3c45fc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/lz.ms @@ -0,0 +1,52 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 0\n20\n0\n1\n1\n1a\n1f\n10\n1e\n + + .include "testutils.inc" + start + moveq -1,r3 + + lz r3,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + moveq 0,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 20 + + move.d 0x80000000,r4 + lz r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x40000000,r4 + lz r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0x7fffffff,r4 + lz r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 42,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1a + + moveq 1,r6 + lz r6,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + move.d 0xffff,r3 + lz r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 10 + + moveq 2,r5 + lz r5,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1e + + quit diff --git a/sim/testsuite/sim/cris/asm/mcp.ms b/sim/testsuite/sim/cris/asm/mcp.ms new file mode 100644 index 00000000000..9aee39ca3fc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mcp.ms @@ -0,0 +1,49 @@ +# mach: crisv32 +# output: fffffffe\n1\n1ffff\nfffffffe\ncc463bdc\n4c463bdc\n0\n + + .include "testutils.inc" + start + +; Set R, clear C. + move 0x100,ccs + moveq -5,r3 + move 2,mof + mcp mof,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + move -1,srp + mcp srp,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move 0xffff,srp + move srp,r3 + mcp srp,r3 + test_cc 0 0 0 0 + dumpr3 ; 1ffff + + move -1,mof + move mof,r3 + mcp mof,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move 0x5432f789,mof + move.d 0x78134452,r3 + mcp mof,r3 + test_cc 1 0 1 0 + dumpr3 ; cc463bdc + + move 0x80000000,srp + mcp srp,r3 + test_cc 0 0 1 0 + dumpr3 ; 4c463bdc + + move 0xb3b9c423,srp + mcp srp,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/movdelsr1.ms b/sim/testsuite/sim/cris/asm/movdelsr1.ms new file mode 100644 index 00000000000..fe33d6707bb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movdelsr1.ms @@ -0,0 +1,33 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: aa117acd\n +# output: eeaabb42\n + +; Bug with move to special register in delay slot, due to +; special flush-insn-cache simulator use. Ordinary move worked; +; special register caused branch to fail. + + .include "testutils.inc" + start + move -1,srp + + move.d 0xaa117acd,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move.d r1,r3 + + fail +0: + dumpr3 + + move.d 0xeeaabb42,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move r1,srp + + fail +0: + move srp,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/movecpc.ms b/sim/testsuite/sim/cris/asm/movecpc.ms new file mode 100644 index 00000000000..cba1c212305 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movecpc.ms @@ -0,0 +1,19 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n + +# We deliberately match both "read from" and "write to" above. + + .include "testutils.inc" + startnostack + moveq -1,r3 + move.b 0x42,pc + dumpr3 + + move.w 0x4321,pc + dumpr3 + + move.d 0x76543210,pc + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movecr.ms b/sim/testsuite/sim/cris/asm/movecr.ms new file mode 100644 index 00000000000..a408747fb56 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movecr.ms @@ -0,0 +1,37 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n + +; Move constant byte, word, dword to register. Check that no extension is +; performed, that only part of the register is set. + + .include "testutils.inc" + startnostack + moveq -1,r3 + move.b 0x42,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + move.b 0x94,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + move.w 0x4321,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq 0,r3 + move.w 0x9234,r3 + test_move_cc 1 0 0 0 + dumpr3 + + move.d 0x76543210,r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movecrt10.ms b/sim/testsuite/sim/cris/asm/movecrt10.ms new file mode 100644 index 00000000000..c9e37047f14 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movecrt10.ms @@ -0,0 +1,17 @@ +#mach: crisv10 +#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n +#output: Basic clock cycles, total @: 22\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "movecr.ms" + +# This test-case is accidentally the same; gets the same cycle +# count as movecrt32.ms, but please keep them separate. diff --git a/sim/testsuite/sim/cris/asm/movecrt32.ms b/sim/testsuite/sim/cris/asm/movecrt32.ms new file mode 100644 index 00000000000..f0aba7fc08a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movecrt32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n +#output: Basic clock cycles, total @: 22\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "movecr.ms" diff --git a/sim/testsuite/sim/cris/asm/movect10.ms b/sim/testsuite/sim/cris/asm/movect10.ms new file mode 100644 index 00000000000..f1e3229ed12 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movect10.ms @@ -0,0 +1,18 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 3\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "testutils.inc" + startnostack + nop + move.d 0xff004567,r5 + break 15 diff --git a/sim/testsuite/sim/cris/asm/movei.ms b/sim/testsuite/sim/cris/asm/movei.ms new file mode 100644 index 00000000000..8d55ae1cb68 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movei.ms @@ -0,0 +1,47 @@ +# mach: crisv32 +# output: fffffffe\n +# output: fffffffe\n + +; Check basic integral-write semantics regarding flags. + + .include "testutils.inc" + start + +; A write that works. Check that flags are set correspondingly. + move.d d,r4 + moveq -2,r5 + setf c + clearf p + move.d [r4],r3 + ax + move.d r5,[r4] + move.d [r4],r3 + + bcc 0f + nop + fail + +0: + dumpr3 ; fffffffe + +; A write that fails; check flags too. + move.d d,r4 + moveq 23,r5 + setf p + clearf c + move.d [r4],r3 + ax + move.d r5,[r4] + move.d [r4],r3 + + bcs 0f + nop + fail + +0: + dumpr3 ; fffffffe + quit + + .data +d: + .dword 42424242 diff --git a/sim/testsuite/sim/cris/asm/movempc.ms b/sim/testsuite/sim/cris/asm/movempc.ms new file mode 100644 index 00000000000..1fd14167469 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movempc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move.d _start,r12 + move.d [r12],pc diff --git a/sim/testsuite/sim/cris/asm/movemr.ms b/sim/testsuite/sim/cris/asm/movemr.ms new file mode 100644 index 00000000000..02f0085f770 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movemr.ms @@ -0,0 +1,79 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 12345678\n10234567\n12345678\n12344567\n12344523\n76543210\nffffffaa\naa\n9911\nffff9911\n78\n56\n3456\n6712\n + + .include "testutils.inc" + start + + .data +mem1: + .dword 0x12345678 +mem2: + .word 0x4567 +mem3: + .byte 0x23 + .dword 0x76543210 + .byte 0xaa,0x11,0x99 + + .text + move.d mem1,r2 + move.d [r2],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d mem2,r3 + move.d [r3],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d mem1,r2 + move.d [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.w [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.b [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.b [r2],r3 + test_move_cc 1 0 0 0 + dumpr3 + + movu.b [r2+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r2],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w [r2+],r3 + test_move_cc 1 0 0 0 + dumpr3 + + move.d mem1,r13 + movs.b [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b [r13],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r13+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + quit + diff --git a/sim/testsuite/sim/cris/asm/movemrv10.ms b/sim/testsuite/sim/cris/asm/movemrv10.ms new file mode 100644 index 00000000000..9fbb878c572 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movemrv10.ms @@ -0,0 +1,101 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: 15\nffff1234\n2\n7\nb\n16\nf\n2\nf\nffffffef\n7\nfffffff4\nf\nfffffff2\nd\n10\nfffffff2\n8\nfffffff4\n + + .include "testutils.inc" + .data +x: + .dword 8,9,10,11 +y: + .dword -12,13,-14,15,16 + + start + moveq 7,r0 + moveq 2,r1 + move.d 0xffff1234,r2 + moveq 21,r3 + move.d x,r4 + setf zcvn + movem r2,[r4+] + test_cc 1 1 1 1 + subq 12,r4 + + dumpr3 ; 15 + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d [r4+],r3 + dumpr3 ; 2 + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d [r4+],r3 + dumpr3 ; b + + subq 16,r4 + moveq 22,r0 + moveq 15,r1 + clearf zcvn + movem r0,[r4] + test_cc 0 0 0 0 + move.d [r4+],r3 + dumpr3 ; 16 + + move.d r1,r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; 2 + + moveq 10,r2 + moveq -17,r0 + clearf zc + setf vn + movem r1,[r4=r4-8] + test_cc 1 0 1 0 + move.d [r4+],r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; ffffffef + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d y,r4 + setf zc + clearf vn + movem [r4+],r3 + test_cc 0 1 0 1 + dumpr3 ; fffffff4 + + move.d r0,r3 + dumpr3 ; f + + move.d r1,r3 + dumpr3 ; fffffff2 + + moveq -12,r1 + + move.d r2,r3 + dumpr3 ; d + + move.d [r4],r3 + dumpr3 ; 10 + + setf zcvn + movem [r5=r4-8],r0 + test_cc 1 1 1 1 + move.d r0,r3 + dumpr3 ; fffffff2 + + sub.d r5,r4 + move.d r4,r3 + dumpr3 ; 8 + + move.d r1,r3 + dumpr3 ; fffffff4 + + quit + diff --git a/sim/testsuite/sim/cris/asm/movemrv32.ms b/sim/testsuite/sim/cris/asm/movemrv32.ms new file mode 100644 index 00000000000..15fcd4cf31b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movemrv32.ms @@ -0,0 +1,97 @@ +# mach: crisv32 +# output: 15\n7\n2\nffff1234\nb\n16\nf\n2\nffffffef\nf\nffff1234\nf\nfffffff4\nd\nfffffff2\n10\nfffffff2\nd\n + + .include "testutils.inc" + .data +x: + .dword 8,9,10,11 +y: + .dword -12,13,-14,15,16 + + start + moveq 7,r0 + moveq 2,r1 + move.d 0xffff1234,r2 + moveq 21,r3 + move.d x,r4 + setf zcvn + movem r2,[r4+] + test_cc 1 1 1 1 + subq 12,r4 + + dumpr3 ; 15 + + move.d [r4+],r3 + dumpr3 ; 7 + + move.d [r4+],r3 + dumpr3 ; 2 + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d [r4+],r3 + dumpr3 ; b + + subq 16,r4 + moveq 22,r0 + moveq 15,r1 + clearf zcvn + movem r0,[r4] + test_cc 0 0 0 0 + move.d [r4+],r3 + dumpr3 ; 16 + + move.d r1,r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; 2 + + subq 8,r4 + moveq 10,r2 + moveq -17,r0 + clearf zc + setf vn + movem r1,[r4] + test_cc 1 0 1 0 + move.d [r4+],r3 + dumpr3 ; ffffffef + + move.d [r4+],r3 + dumpr3 ; f + + move.d [r4+],r3 + dumpr3 ; ffff1234 + + move.d y,r4 + setf zc + clearf vn + movem [r4+],r3 + test_cc 0 1 0 1 + dumpr3 ; f + + move.d r0,r3 + dumpr3 ; fffffff4 + + move.d r1,r3 + dumpr3 ; d + + move.d r2,r3 + dumpr3 ; fffffff2 + + move.d [r4],r3 + dumpr3 ; 10 + + subq 8,r4 + setf zcvn + movem [r4+],r0 + test_cc 1 1 1 1 + move.d r0,r3 + dumpr3 ; fffffff2 + + move.d r1,r3 + dumpr3 ; d + + quit + diff --git a/sim/testsuite/sim/cris/asm/movepcb.ms b/sim/testsuite/sim/cris/asm/movepcb.ms new file mode 100644 index 00000000000..0dcc396d3b0 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movepcb.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + test.b pc + quit diff --git a/sim/testsuite/sim/cris/asm/movepcd.ms b/sim/testsuite/sim/cris/asm/movepcd.ms new file mode 100644 index 00000000000..240db55d3ba --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movepcd.ms @@ -0,0 +1,16 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n + +# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally, +# the output message should say "read" of PC, but we allow PC as source in +# a move.d r,R insn, so there's no logical way to get that, short of a +# special pattern, which would be just too ugly. The output message says +# "write", but let's match "read" too so we won't fail if things suddenly +# improve. + + .include "testutils.inc" + startnostack + setf + test.d pc + quit diff --git a/sim/testsuite/sim/cris/asm/movepcw.ms b/sim/testsuite/sim/cris/asm/movepcw.ms new file mode 100644 index 00000000000..d51b0d9c0c7 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movepcw.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + test.w pc + quit diff --git a/sim/testsuite/sim/cris/asm/moveq.ms b/sim/testsuite/sim/cris/asm/moveq.ms new file mode 100644 index 00000000000..121cbda9d7e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moveq.ms @@ -0,0 +1,15 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# sim: --trace-core=on +# ld: --section-start=.text=0 +# output: read-2 exec:0x00000002 -> 0x3262\nread-2 exec:0x00000004 -> 0xe93e\nffffffe2\nread-2 exec:0x00000006 -> 0x324d\nread-2 exec:0x00000008 -> 0xe93e\nd\nread-2 exec:0x0000000a -> 0xe93f\n + +; Output a positive and a negative number, set from moveq. + + .include "testutils.inc" + startnostack + moveq -30,r3 + dumpr3 + moveq 13,r3 + dumpr3 + quit + diff --git a/sim/testsuite/sim/cris/asm/moveqpc.ms b/sim/testsuite/sim/cris/asm/moveqpc.ms new file mode 100644 index 00000000000..dea5106ab05 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moveqpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + moveq -30,pc + quit diff --git a/sim/testsuite/sim/cris/asm/mover.ms b/sim/testsuite/sim/cris/asm/mover.ms new file mode 100644 index 00000000000..57b1d884232 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mover.ms @@ -0,0 +1,29 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff05\nffff0005\n5\nffffff00\n + +; Move between registers. Check that just the subreg is copied. + + .include "testutils.inc" + startnostack + moveq -30,r3 + moveq 5,r4 + move.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 + + move.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 + + move.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + moveq 0,r4 + move.b r4,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit + diff --git a/sim/testsuite/sim/cris/asm/moverbpc.ms b/sim/testsuite/sim/cris/asm/moverbpc.ms new file mode 100644 index 00000000000..34a1f3c0188 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverbpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/sim/cris/asm/moverdpc.ms b/sim/testsuite/sim/cris/asm/moverdpc.ms new file mode 100644 index 00000000000..34a1f3c0188 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverdpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/sim/cris/asm/moverm.ms b/sim/testsuite/sim/cris/asm/moverm.ms new file mode 100644 index 00000000000..be8126f3440 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverm.ms @@ -0,0 +1,45 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 7823fec2\n10231879\n102318fe\n + + .include "testutils.inc" + start + + .data +mem1: + .dword 0x12345678 +mem2: + .word 0x4567 +mem3: + .byte 0x23 + .dword 0x76543210 + .byte 0xaa,0x11,0x99 + + .text + move.d mem1,r2 + move.d 0x7823fec2,r4 + setf nzvc + move.d r4,[r2+] + test_cc 1 1 1 1 + subq 4,r2 + move.d [r2],r3 + dumpr3 ; 7823fec2 + + move.d mem2,r3 + move.d 0x45231879,r4 + clearf nzvc + move.w r4,[r3] + test_cc 0 0 0 0 + move.d [r3],r3 + dumpr3 ; 10231879 + + move.d mem2,r2 + moveq -2,r4 + clearf nc + setf zv + move.b r4,[r2+] + test_cc 0 1 1 0 + subq 1,r2 + move.d [r2],r3 + dumpr3 ; 102318ff + + quit diff --git a/sim/testsuite/sim/cris/asm/moverpcb.ms b/sim/testsuite/sim/cris/asm/moverpcb.ms new file mode 100644 index 00000000000..d95d9dafcb1 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverpcb.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + move.b pc,r5 + quit diff --git a/sim/testsuite/sim/cris/asm/moverpcd.ms b/sim/testsuite/sim/cris/asm/moverpcd.ms new file mode 100644 index 00000000000..b7a54ea547d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverpcd.ms @@ -0,0 +1,13 @@ +# mach: crisv3 crisv8 crisv10 +# output: 4\n + +# Test that move.d pc,R works. + + .include "testutils.inc" + start +x: + move.d pc,r3 +y: + sub.d y-4,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/moverpcw.ms b/sim/testsuite/sim/cris/asm/moverpcw.ms new file mode 100644 index 00000000000..88681fb505a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverpcw.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + move.w pc,r2 + quit diff --git a/sim/testsuite/sim/cris/asm/moverwpc.ms b/sim/testsuite/sim/cris/asm/moverwpc.ms new file mode 100644 index 00000000000..34a1f3c0188 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/moverwpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + startnostack + setf + move.d r5,pc + quit diff --git a/sim/testsuite/sim/cris/asm/movesmp.ms b/sim/testsuite/sim/cris/asm/movesmp.ms new file mode 100644 index 00000000000..a85dfc8f85b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movesmp.ms @@ -0,0 +1,28 @@ +# mach: crisv3 crisv8 crisv10 +# output: bed0bed1\nabedab0d\nbed0bed1\n + +# Test that move to and from special register and memory clears the +# "prefixed" bit. + + .include "testutils.inc" + .data +w: + .dword 0 +y: + .dword 0xbed0bed1 +z: + .dword 0xabedab0d + + start +x: + move.d y,r3 + clear.d [w] + move.d [r3],r3 + dumpr3 ; bed0bed1 + move.d z,r3 + move [w+4],srp + move.d [r3],r3 + dumpr3 ; abedab0d + move srp,r3 + dumpr3 ; bed0bed1 + quit diff --git a/sim/testsuite/sim/cris/asm/movmp.ms b/sim/testsuite/sim/cris/asm/movmp.ms new file mode 100644 index 00000000000..7080d71f713 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movmp.ms @@ -0,0 +1,116 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n + +# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with +# functionality common to all models. + + .include "testutils.inc" + start + + .data +filler: + .byte 0xaa + .word 0x4433 + .dword 0x55778866 + .byte 0xcc + + .text +; Test that writing to zero-registers is a nop + move 0xaa,p0 + move 0x4433,p4 + move 0x55774433,p8 + moveq -1,r3 + setf zcvn + clear.b r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + clearf zcvn + clear.w r3 + test_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; "Write" using ordinary memory references too. + move.d filler,r6 + move [r6],p0 + move [r6],p4 + move [r6],p8 + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; And postincremented. + move [r6+],p0 + move [r6+],p4 + move [r6+],p8 + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + +; Now see that we can write to the registers too. + +; [PC+] + move.d filler,r9 + move 0xbb113344,srp + move srp,r3 + dumpr3 + +; [R+] + move [r9+],srp + move srp,r3 + dumpr3 + +; [R] + move [r9],srp + move srp,r3 + dumpr3 + +; And check writing to memory, clear and srp. + + move.d filler,r9 + move 0xabcde012,srp + setf zcvn + move srp,[r9+] + test_cc 1 1 1 1 + subq 4,r9 + move.d [r9],r3 + dumpr3 + + clearf zcvn + clear.b [r9] + test_cc 0 0 0 0 + move.d [r9],r3 + dumpr3 + + addq 2,r9 + clear.w [r9+] + subq 2,r9 + move.d [r9],r3 + dumpr3 + + clear.d [r9] + move.d [r9],r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movpmv10.ms b/sim/testsuite/sim/cris/asm/movpmv10.ms new file mode 100644 index 00000000000..72dcee739dc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movpmv10.ms @@ -0,0 +1,35 @@ +# mach: crisv10 +# output: 1122330a\nbb113344\naa557711\n + +# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. + + .include "testutils.inc" + start + .data +store: + .dword 0x11223344 + .dword 0x77665544 + + .text + moveq -1,r3 + move.d store,r4 + clearf zcvn + move vr,[r4] + test_cc 0 0 0 0 + move [r4+],mof + move mof,r3 + dumpr3 + + moveq -1,r3 + move 0xbb113344,mof + move mof,r3 + dumpr3 + + move 0xaa557711,mof + setf zcvn + move mof,[r4] + test_cc 1 1 1 1 + move.d [r4],r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movpmv32.ms b/sim/testsuite/sim/cris/asm/movpmv32.ms new file mode 100644 index 00000000000..6d173382a5b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movpmv32.ms @@ -0,0 +1,35 @@ +# mach: crisv32 +# output: 11223320\nbb113344\naa557711\n + +# Test v32-specific special registers. FIXME: more registers. + + .include "testutils.inc" + start + .data +store: + .dword 0x11223344 + .dword 0x77665544 + + .text + moveq -1,r3 + move.d store,r4 + move vr,[r4] + move [r4+],mof + move mof,r3 + dumpr3 + + moveq -1,r3 + clearf zcvn + move 0xbb113344,mof + test_cc 0 0 0 0 + move mof,r3 + dumpr3 + + setf zcvn + move 0xaa557711,mof + test_cc 1 1 1 1 + move mof,[r4] + move.d [r4],r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movppc.ms b/sim/testsuite/sim/cris/asm/movppc.ms new file mode 100644 index 00000000000..e100e25dd75 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movppc.ms @@ -0,0 +1,7 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move srp,[PC+] diff --git a/sim/testsuite/sim/cris/asm/movpr.ms b/sim/testsuite/sim/cris/asm/movpr.ms new file mode 100644 index 00000000000..4279a732d5a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movpr.ms @@ -0,0 +1,28 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\nffff0000\n0\nbb113344\n + +# Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with +# functionality common to all models. + + .include "testutils.inc" + start + moveq -1,r3 + clear.b r3 + dumpr3 + + moveq -1,r3 + clear.w r3 + dumpr3 + + moveq -1,r3 + clear.d r3 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + setf zcvn + move r4,srp + move srp,r3 + test_cc 1 1 1 1 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/movprv10.ms b/sim/testsuite/sim/cris/asm/movprv10.ms new file mode 100644 index 00000000000..29a10b599f1 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movprv10.ms @@ -0,0 +1,21 @@ +# mach: crisv10 +# output: ffffff0a\nbb113344\n + +# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. + + .include "testutils.inc" + start + moveq -1,r3 + setf zcvn + move vr,r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + clearf zcvn + move r4,mof + move mof,r3 + test_cc 0 0 0 0 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/movprv32.ms b/sim/testsuite/sim/cris/asm/movprv32.ms new file mode 100644 index 00000000000..5a2f4dd2d67 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movprv32.ms @@ -0,0 +1,21 @@ +# mach: crisv32 +# output: ffffff20\nbb113344\n + +# Test v32-specific special registers. FIXME: more registers. + + .include "testutils.inc" + start + moveq -1,r3 + setf zcvn + move vr,r3 + test_cc 1 1 1 1 + dumpr3 + + moveq -1,r3 + move.d 0xbb113344,r4 + clearf cvnz + move r4,mof + test_cc 0 0 0 0 + move mof,r3 + dumpr3 + quit diff --git a/sim/testsuite/sim/cris/asm/movrss.ms b/sim/testsuite/sim/cris/asm/movrss.ms new file mode 100644 index 00000000000..964c1611483 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movrss.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# xerror: +# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move R3,S0 + diff --git a/sim/testsuite/sim/cris/asm/movscpc.ms b/sim/testsuite/sim/cris/asm/movscpc.ms new file mode 100644 index 00000000000..a753e236347 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movscpc.ms @@ -0,0 +1,13 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + movs.b 0x42,pc + dumpr3 + + movs.w 0x4321,pc + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movscr.ms b/sim/testsuite/sim/cris/asm/movscr.ms new file mode 100644 index 00000000000..457cca8979e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movscr.ms @@ -0,0 +1,29 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 42\nffffff85\n7685\nffff8765\n0\n + +; Move constant byte, word, dword to register. Check that sign-extension +; is performed. + + .include "testutils.inc" + start + moveq -1,r3 + movs.b 0x42,r3 + dumpr3 + + movs.b 0x85,r3 + test_move_cc 1 0 0 0 + dumpr3 + + movs.w 0x7685,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movs.w 0x8765,r3 + test_move_cc 1 0 0 0 + dumpr3 + + movs.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movsm.ms b/sim/testsuite/sim/cris/asm/movsm.ms new file mode 100644 index 00000000000..59973d1f352 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movsm.ms @@ -0,0 +1,44 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nfffffff5\n5\nfffffff5\n0\n + +; Movs between registers. Check that sign-extension is performed and the +; full register is set. + + .include "testutils.inc" + + .data +x: + .byte 5,-11 + .word 5,-11 + .word 0 + + start + move.d x,r5 + + moveq -1,r3 + movs.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + movs.b [r5],r3 + test_move_cc 1 0 0 0 + addq 1,r5 + dumpr3 + + moveq -1,r3 + movs.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r3 + movs.w [r5],r3 + test_move_cc 1 0 0 0 + addq 2,r5 + dumpr3 + + movs.w [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movsmpc.ms b/sim/testsuite/sim/cris/asm/movsmpc.ms new file mode 100644 index 00000000000..16d818b8d30 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movsmpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move.d _start,r12 + movs.w [r12],pc diff --git a/sim/testsuite/sim/cris/asm/movsr.ms b/sim/testsuite/sim/cris/asm/movsr.ms new file mode 100644 index 00000000000..283975fac64 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movsr.ms @@ -0,0 +1,46 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nfffffff5\n5\nfffffff5\n0\n + +; Movs between registers. Check that sign-extension is performed and the +; full register is set. + + .include "testutils.inc" + start + moveq -1,r5 + moveq 5,r4 + move.b r4,r5 + moveq -1,r3 + movs.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.b r4,r5 + moveq 0,r3 + movs.b r5,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq -1,r5 + moveq 5,r4 + move.w r4,r5 + moveq -1,r3 + movs.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.w r4,r5 + moveq 0,r3 + movs.w r5,r3 + test_move_cc 1 0 0 0 + dumpr3 + + moveq 0,r5 + movs.b r5,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movsrpc.ms b/sim/testsuite/sim/cris/asm/movsrpc.ms new file mode 100644 index 00000000000..fccf31a1ce8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movsrpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + setf + movs.w r0,pc + quit diff --git a/sim/testsuite/sim/cris/asm/movssr.ms b/sim/testsuite/sim/cris/asm/movssr.ms new file mode 100644 index 00000000000..62663c1c04a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movssr.ms @@ -0,0 +1,8 @@ +# mach: crisv32 +# xerror: +# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move S0,R3 + diff --git a/sim/testsuite/sim/cris/asm/movucpc.ms b/sim/testsuite/sim/cris/asm/movucpc.ms new file mode 100644 index 00000000000..91fe4de8767 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movucpc.ms @@ -0,0 +1,10 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + movu.w 0x4321,pc + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movucr.ms b/sim/testsuite/sim/cris/asm/movucr.ms new file mode 100644 index 00000000000..7508ff8c64b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movucr.ms @@ -0,0 +1,33 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 42\n85\n7685\n8765\n0\n + +; Move constant byte, word, dword to register. Check that zero-extension +; is performed. + + .include "testutils.inc" + start + moveq -1,r3 + movu.b 0x42,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.b 0x85,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.w 0x7685,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r3 + movu.w 0x8765,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movum.ms b/sim/testsuite/sim/cris/asm/movum.ms new file mode 100644 index 00000000000..c6ea625fd74 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movum.ms @@ -0,0 +1,40 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nf5\n5\nfff5\n0\n + +; Movu between registers. Check that zero-extension is performed and the +; full register is set. + + .include "testutils.inc" + + .data +x: + .byte 5,-11 + .word 5,-11 + .word 0 + + start + move.d x,r5 + + movu.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.b [r5],r3 + test_move_cc 0 0 0 0 + addq 1,r5 + dumpr3 + + movu.w [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w [r5],r3 + test_move_cc 0 0 0 0 + addq 2,r5 + dumpr3 + + movu.w [r5],r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movumpc.ms b/sim/testsuite/sim/cris/asm/movumpc.ms new file mode 100644 index 00000000000..eecddf2b744 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movumpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + move.d _start,r1 + movu.b [r1+],pc diff --git a/sim/testsuite/sim/cris/asm/movur.ms b/sim/testsuite/sim/cris/asm/movur.ms new file mode 100644 index 00000000000..a46d54de16d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movur.ms @@ -0,0 +1,45 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 5\nf5\n5\nfff5\n0\n + +; Movu between registers. Check that zero-extension is performed and the +; full register is set. + + .include "testutils.inc" + start + moveq -1,r5 + moveq 5,r4 + move.b r4,r5 + moveq -1,r3 + movu.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.b r4,r5 + moveq -1,r3 + movu.b r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq -1,r5 + moveq 5,r4 + move.w r4,r5 + moveq -1,r3 + movu.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + moveq 0,r5 + moveq -11,r4 + move.w r4,r5 + moveq -1,r3 + movu.w r5,r3 + test_move_cc 0 0 0 0 + dumpr3 + + movu.w 0,r3 + test_move_cc 0 1 0 0 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/movurpc.ms b/sim/testsuite/sim/cris/asm/movurpc.ms new file mode 100644 index 00000000000..a90c49282ab --- /dev/null +++ b/sim/testsuite/sim/cris/asm/movurpc.ms @@ -0,0 +1,9 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + setf + movu.b r3,pc + quit diff --git a/sim/testsuite/sim/cris/asm/mstep.ms b/sim/testsuite/sim/cris/asm/mstep.ms new file mode 100644 index 00000000000..74aa20d78cd --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mstep.ms @@ -0,0 +1,108 @@ +# mach: crisv3 crisv8 crisv10 +#output: fffffffe\n +#output: 3\n +#output: 1fffe\n +#output: 2fffd\n +#output: fffffffd\n +#output: ffffffff\n +#output: f02688a4\n +#output: 1fffe\n +#output: fffffffe\n +#output: fffffffe\n +#output: fffffff9\n +#output: 0\n +#output: 4459802d\n +#output: 4459802d\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + moveq -1,r4 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xffff,r4 + move.d r4,r3 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0xffff,r4 + move.d r4,r3 + setf n + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2fffd + + moveq -1,r4 + move.d r4,r3 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffd + + moveq -1,r3 + moveq 1,r4 + setf n + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mstep r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; f02688a4 + + move.d 0xffff,r3 + move.d 0x1fffe,r4 + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1fffe + + move.d 0x7fffffff,r3 + moveq 5,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x7fffffff,r3 + moveq 0,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x7fffffff,r3 + moveq -5,r5 + mstep r5,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffff9 + + move.d 0x7fffffff,r3 + moveq 2,r5 + setf n + mstep r5,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + setf n + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4459802d + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + setf nc + mstep r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4459802d + + quit diff --git a/sim/testsuite/sim/cris/asm/msteppc1.ms b/sim/testsuite/sim/cris/asm/msteppc1.ms new file mode 100644 index 00000000000..5c78e0b34ac --- /dev/null +++ b/sim/testsuite/sim/cris/asm/msteppc1.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5.\n + + .include "testutils.inc" + start + mstep pc,r2 diff --git a/sim/testsuite/sim/cris/asm/msteppc2.ms b/sim/testsuite/sim/cris/asm/msteppc2.ms new file mode 100644 index 00000000000..e78be45c0a5 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/msteppc2.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5.\n + + .include "testutils.inc" + start + mstep r2,pc diff --git a/sim/testsuite/sim/cris/asm/msteppc3.ms b/sim/testsuite/sim/cris/asm/msteppc3.ms new file mode 100644 index 00000000000..9e6d30124b8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/msteppc3.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\n +# output: program stopped with signal 5.\n + + .include "testutils.inc" + start + mstep pc,pc diff --git a/sim/testsuite/sim/cris/asm/mulv10.ms b/sim/testsuite/sim/cris/asm/mulv10.ms new file mode 100644 index 00000000000..43511f7ad9b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mulv10.ms @@ -0,0 +1,29 @@ +# mach: crisv8 crisv10 +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n + +; Check that carry is cleared on v8, v10. + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + setf c + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + setf c + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + quit diff --git a/sim/testsuite/sim/cris/asm/mulv32.ms b/sim/testsuite/sim/cris/asm/mulv32.ms new file mode 100644 index 00000000000..6d2edcb3115 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mulv32.ms @@ -0,0 +1,51 @@ +# mach: crisv32 +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n +# output: fffffffe\n +# output: ffffffff\n +# output: fffffffe\n +# output: 1\n + +; Check that carry is not modified on v32. + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + setf c + muls.d r4,r3 + test_cc 1 0 0 1 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + setf c + mulu.d r4,r3 + test_cc 0 0 1 1 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + moveq -1,r3 + moveq 2,r4 + clearf c + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + clearf c + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + quit diff --git a/sim/testsuite/sim/cris/asm/mulx.ms b/sim/testsuite/sim/cris/asm/mulx.ms new file mode 100644 index 00000000000..1fc62619d01 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/mulx.ms @@ -0,0 +1,246 @@ +# mach: crisv10 crisv32 +# output: fffffffe\nffffffff\nfffffffe\n1\nfffffffe\nffffffff\nfffffffe\n1\nfffe0001\n0\nfffe0001\n0\n1\n0\n1\nfffffffe\n193eade2\n277e3a49\n193eade2\n277e3a49\nfffffffe\nffffffff\n1fffe\n0\nfffffffe\nffffffff\n1fffe\n0\n1\n0\nfffe0001\n0\nfdbdade2\nffffffff\n420fade2\n0\nfffffffe\nffffffff\n1fe\n0\nfffffffe\nffffffff\n1fe\n0\n1\n0\nfe01\n0\n1\n0\nfe01\n0\nffffd9e2\nffffffff\n2be2\n0\n0\n0\n0\n0\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq 2,r4 + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + moveq 2,r3 + moveq -1,r4 + muls.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; 1 + + move.d 0xffff,r4 + move.d r4,r3 + muls.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + move.d 0xffff,r4 + move.d r4,r3 + mulu.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + muls.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.d r4,r3 + test_cc 1 0 1 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; fffffffe + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 193eade2 + move mof,r3 + dumpr3 ; 277e3a49 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.d r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 193eade2 + move mof,r3 + dumpr3 ; 277e3a49 + + move.d 0xffff,r3 + moveq 2,r4 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + move mof,r3 + dumpr3 ; 0 + + moveq 2,r3 + move.d 0xffff,r4 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fffe + move mof,r3 + dumpr3 ; 0 + + move.d 0xffff,r4 + move.d r4,r3 + muls.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fffe0001 + move mof,r3 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fdbdade2 + move mof,r3 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 420fade2 + move mof,r3 + dumpr3 ; 0 + + move.d 0xff,r3 + moveq 2,r4 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq -1,r3 + moveq 2,r4 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fe + move mof,r3 + dumpr3 ; 0 + + moveq 2,r3 + moveq -1,r4 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + move mof,r3 + dumpr3 ; ffffffff + + moveq 2,r3 + moveq -1,r4 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1fe + move mof,r3 + dumpr3 ; 0 + + move.d 0xff,r4 + move.d r4,r3 + muls.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + moveq -1,r4 + move.d r4,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fe01 + move mof,r3 + dumpr3 ; 0 + + move.d 0xfeda49ff,r4 + move.d r4,r3 + muls.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + move mof,r3 + dumpr3 ; 0 + + move.d 0xfeda49ff,r4 + move.d r4,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; fe01 + move mof,r3 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + muls.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffd9e2 + move mof,r3 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + mulu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 2be2 + move mof,r3 + dumpr3 ; 0 + + moveq 0,r3 + move.d 0xf87f4aeb,r4 + muls.d r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + move mof,r3 + dumpr3 ; 0 + + move.d 0xf87f4aeb,r3 + moveq 0,r4 + mulu.d r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + move mof,r3 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/neg.ms b/sim/testsuite/sim/cris/asm/neg.ms new file mode 100644 index 00000000000..f2681ea979f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/neg.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: ffffffff\nffffffff\n0\n80000000\n1\nba987655\nffff\nffff\n0\n89ab8000\nffff0001\n45677655\nff\nff\n0\n89abae80\nffffff01\n45678955\n + + .include "testutils.inc" + start + moveq 0,r3 + moveq 1,r4 + neg.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 1,r3 + moveq 0,r4 + neg.d r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 0,r3 + neg.d r3,r3 + test_move_cc 0 0 1 0 + dumpr3 ; 0 + + move.d 0x80000000,r3 + neg.d r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 80000000 + + moveq -1,r3 + neg.d r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0x456789ab,r3 + neg.d r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ba987655 + + moveq 0,r3 + moveq 1,r4 + neg.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff + + moveq 1,r3 + moveq 0,r4 + neg.w r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff + + moveq 0,r3 + neg.w r3,r3 + test_move_cc 0 0 1 0 + dumpr3 ; 0 + + move.d 0x89ab8000,r3 + neg.w r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 89ab8000 + + moveq -1,r3 + neg.w r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0001 + + move.d 0x456789ab,r3 + neg.w r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 45677655 + + moveq 0,r3 + moveq 1,r4 + neg.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ff + + moveq 1,r3 + moveq 0,r4 + neg.b r3,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ff + + moveq 0,r3 + neg.b r3,r3 + test_move_cc 0 0 1 0 + dumpr3 ; 0 + + move.d 0x89abae80,r3 + neg.b r3,r3 + test_move_cc 0 0 1 0 + dumpr3 ; 89abae80 + + moveq -1,r3 + neg.b r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffffff01 + + move.d 0x456789ab,r3 + neg.b r3,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 45678955 + + quit diff --git a/sim/testsuite/sim/cris/asm/nopv10t.ms b/sim/testsuite/sim/cris/asm/nopv10t.ms new file mode 100644 index 00000000000..d96eaf09b51 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/nopv10t.ms @@ -0,0 +1,13 @@ +#mach: crisv0 crisv3 crisv8 crisv10 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t.ms b/sim/testsuite/sim/cris/asm/nopv32t.ms new file mode 100644 index 00000000000..794d19b45b5 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/nopv32t.ms @@ -0,0 +1,21 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + .global _start +_start: + nop + nop + nop + nop + nop + break 15 diff --git a/sim/testsuite/sim/cris/asm/nopv32t2.ms b/sim/testsuite/sim/cris/asm/nopv32t2.ms new file mode 100644 index 00000000000..760a53936fd --- /dev/null +++ b/sim/testsuite/sim/cris/asm/nopv32t2.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: Clock cycles including stall cycles for unaligned accesses @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=unaligned + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t3.ms b/sim/testsuite/sim/cris/asm/nopv32t3.ms new file mode 100644 index 00000000000..d8b2351a190 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/nopv32t3.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: Schedulable clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=schedulable + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/nopv32t4.ms b/sim/testsuite/sim/cris/asm/nopv32t4.ms new file mode 100644 index 00000000000..98f336b52dc --- /dev/null +++ b/sim/testsuite/sim/cris/asm/nopv32t4.ms @@ -0,0 +1,13 @@ +#mach: crisv10 crisv32 +#output: All accounted clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=all + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/not.ms b/sim/testsuite/sim/cris/asm/not.ms new file mode 100644 index 00000000000..4416bbc632c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/not.ms @@ -0,0 +1,31 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: fffffffe\nfffffffd\nffff0f00\n0\n87ecbbad\n + + .include "testutils.inc" + start + moveq 1,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffe + + moveq 2,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; fffffffd + + move.d 0xf0ff,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffff0f00 + + moveq -1,r3 + not r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + not r3 + test_move_cc 1 0 0 0 + dumpr3 ; 87ecbbad + + quit diff --git a/sim/testsuite/sim/cris/asm/op3.ms b/sim/testsuite/sim/cris/asm/op3.ms new file mode 100644 index 00000000000..44fa83a7981 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/op3.ms @@ -0,0 +1,98 @@ +# mach: crisv0 crisv3 crisv8 crisv10 +# output: ee19cd0b\nee197761\nccff2244\n55aa77ff\nffffaa77\naa\n4243ab11\n424377ab\nfdedaaf0\n4242dd68\n4242dd68\n40025567\n57eb77ff\n55aa77ff\n + + .include "testutils.inc" + .data +x: + .dword 0x55aa77ff + .dword 0xccff2244 + .dword 0x88ccee19 + + start + move.d x,r10 + moveq 0,r3 + moveq 12,r4 + add.d [r10+6],r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ee19cd0b + + move.d 0x1267,r7 + subu.w [r10+2],r3,r8 + test_cc 1 0 0 0 + move.d r8,r3 + dumpr3 ; ee197761 + + moveq 1,r8 + bound.d [r10+r8.d],r3,r5 + test_move_cc 1 0 0 0 + move.d r5,r3 + dumpr3 ; ccff2244 + +; Also applies to move insns. Bleah. + moveq 0,r5 + bdap 0,r10 + move.d [r3],r5 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + moveq 0,r5 + bdap 1,r10 + movs.w [r3],r5 + test_move_cc 1 0 0 0 + dumpr3 ; ffffaa77 + + moveq 0,r5 + bdap 2,r10 + test_move_cc 0 0 0 0 + movu.b [r3],r5 + dumpr3 ; aa + + move.d 0x42435567,r8 + bdap 2,r10 + adds.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4243ab11 + + move.d 0x42435567,r8 + bdap 4,r10 + addu.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 424377ab + + move.d 0x42435567,r8 + bdap 1,r10 + sub.d [r3],r8 + test_cc 1 0 0 1 + dumpr3 ; fdedaaf0 + + move.d 0x42435567,r8 + bdap 0,r10 + subs.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4242dd68 + + move.d 0x42435567,r8 + bdap 0,r10 + subu.w [r3],r8 + test_cc 0 0 0 0 + dumpr3 ; 4242dd68 + + move.d 0x42435567,r8 + bdap 0,r10 + and.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 40025567 + + move.d 0x42435567,r8 + bdap 0,r10 + or.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 57eb77ff + + move.d 0xc2435567,r8 + bdap 0,r10 + bound.d [r3],r8 + test_move_cc 0 0 0 0 + dumpr3 ; 55aa77ff + + quit diff --git a/sim/testsuite/sim/cris/asm/opterr1.ms b/sim/testsuite/sim/cris/asm/opterr1.ms new file mode 100644 index 00000000000..be40107f14a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/opterr1.ms @@ -0,0 +1,5 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: *: unrecognized option `--cris-stats=xyz'\n +# sim: --cris-stats=xyz + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/opterr2.ms b/sim/testsuite/sim/cris/asm/opterr2.ms new file mode 100644 index 00000000000..dc866dd93ef --- /dev/null +++ b/sim/testsuite/sim/cris/asm/opterr2.ms @@ -0,0 +1,5 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# xerror: +# output: *: unrecognized option `--cris-xyz'\n +# sim: --cris-xyz + .include "nopv32t.ms" diff --git a/sim/testsuite/sim/cris/asm/option1.ms b/sim/testsuite/sim/cris/asm/option1.ms new file mode 100644 index 00000000000..387a01ffdd0 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/option1.ms @@ -0,0 +1,7 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --cris-trace=foo +#xerror: +#output: Unknown option `--cris-trace=foo'\n + .include "testutils.inc" + start + fail diff --git a/sim/testsuite/sim/cris/asm/option2.ms b/sim/testsuite/sim/cris/asm/option2.ms new file mode 100644 index 00000000000..4ac6a86706b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/option2.ms @@ -0,0 +1,5 @@ +#mach: crisv0 crisv3 crisv8 crisv10 crisv32 +#sim: --sysroot=/non/exist/dir +#output: run: can't change directory to "/non/exist/dir"\n +#xerror: + .include "option1.ms" diff --git a/sim/testsuite/sim/cris/asm/orc.ms b/sim/testsuite/sim/cris/asm/orc.ms new file mode 100644 index 00000000000..d8fbe700f7a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/orc.ms @@ -0,0 +1,71 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + start + moveq 1,r3 + or.d 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.d 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + or.d 0xff0f,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r3 + or.d -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + or.d 0x5432f789,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + or.w 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0003 + + moveq 2,r3 + or.w 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + or.w 0xff5f,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + or.w 0xf789,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + or.b 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.b 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfa3,r3 + or.b 0x4a,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x78134453,r3 + or.b 0x89,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/sim/cris/asm/orm.ms b/sim/testsuite/sim/cris/asm/orm.ms new file mode 100644 index 00000000000..f2bdaae255e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/orm.ms @@ -0,0 +1,75 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + .data +x: + .dword 2,1,0xff0f,-1,0x5432f789 + .word 2,1,0xff5f,0xf789 + .byte 2,1,0x4a,0x89 + + start + moveq 1,r3 + move.d x,r5 + or.d [r5+],r3 + dumpr3 ; 3 + + moveq 2,r3 + or.d [r5],r3 + addq 4,r5 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + or.d [r5+],r3 + dumpr3 ; ffff + + moveq -1,r3 + or.d [r5+],r3 + dumpr3 ; ffffffff + + move.d 0x78134452,r3 + or.d [r5+],r3 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + or.w [r5+],r3 + dumpr3 ; ffff0003 + + moveq 2,r3 + or.w [r5],r3 + addq 2,r5 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + or.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x78134452,r3 + or.w [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + or.b [r5+],r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + or.b [r5],r3 + addq 1,r5 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfa3,r3 + or.b [r5+],r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x78134453,r3 + or.b [r5],r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/sim/cris/asm/orq.ms b/sim/testsuite/sim/cris/asm/orq.ms new file mode 100644 index 00000000000..905a9612d03 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/orq.ms @@ -0,0 +1,41 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffffff\nffffffff\n1f\nffffffe0\n7813445e\n + + .include "testutils.inc" + start + moveq 1,r3 + orq 2,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + orq 1,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xf0ff,r3 + orq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 0,r3 + orq -1,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + moveq 0,r3 + orq 31,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1f + + moveq 0,r3 + orq -32,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffe0 + + move.d 0x78134452,r3 + orq 12,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7813445e + + quit diff --git a/sim/testsuite/sim/cris/asm/orr.ms b/sim/testsuite/sim/cris/asm/orr.ms new file mode 100644 index 00000000000..54d033b68bb --- /dev/null +++ b/sim/testsuite/sim/cris/asm/orr.ms @@ -0,0 +1,84 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n + + .include "testutils.inc" + start + moveq 1,r3 + moveq 2,r4 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xff0f,r4 + move.d 0xf0ff,r3 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff + + moveq -1,r4 + move.d r4,r3 + or.d r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + or.d r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 7c33f7db + + move.d 0xffff0001,r3 + moveq 2,r4 + or.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ffff0003 + + moveq 2,r3 + move.d 0xffff0001,r4 + or.w r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xfedaffaf,r3 + move.d 0xffffff5f,r4 + or.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; fedaffff + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + or.w r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 7813f7db + + moveq 1,r3 + move.d 0xffffff02,r4 + or.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + or.b r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0x4a,r4 + move.d 0xfa3,r3 + or.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; feb + + move.d 0x5432f789,r4 + move.d 0x78134453,r3 + or.b r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; 781344db + + quit diff --git a/sim/testsuite/sim/cris/asm/raw1.ms b/sim/testsuite/sim/cris/asm/raw1.ms new file mode 100644 index 00000000000..fd2fcb20f6b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw1.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: read-then-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d [$r0],$r2 + move.d [$r1],$r4 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw10.ms b/sim/testsuite/sim/cris/asm/raw10.ms new file mode 100644 index 00000000000..a9faee94d7c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw10.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: swrite-then-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + move [$r1],$srp + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw11.ms b/sim/testsuite/sim/cris/asm/raw11.ms new file mode 100644 index 00000000000..38bf2744228 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw11.ms @@ -0,0 +1,23 @@ +; Checking read-after-write: swrite-then-nop-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + nop + move [$r1],$srp + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw12.ms b/sim/testsuite/sim/cris/asm/raw12.ms new file mode 100644 index 00000000000..d8ffa458d1b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw12.ms @@ -0,0 +1,24 @@ +; Checking read-after-write: swrite-then-nop-nop-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + clear.d [$r0] + nop + nop + move [$r1],$srp + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw13.ms b/sim/testsuite/sim/cris/asm/raw13.ms new file mode 100644 index 00000000000..a4175c477df --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw13.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-WZ-then-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move [$r0],$wz + move [$r1],$srp + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw14.ms b/sim/testsuite/sim/cris/asm/raw14.ms new file mode 100644 index 00000000000..f08632869a5 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw14.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "schedulable". +#mach: crisv32 +#output: Schedulable clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=schedulable + .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw15.ms b/sim/testsuite/sim/cris/asm/raw15.ms new file mode 100644 index 00000000000..3f490675f18 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw15.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "all". +#mach: crisv32 +#output: All accounted clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=all + .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw16.ms b/sim/testsuite/sim/cris/asm/raw16.ms new file mode 100644 index 00000000000..07977cc29ae --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw16.ms @@ -0,0 +1,14 @@ +; Checking read-after-write: cycles included in "unaligned". +#mach: crisv32 +#output: Clock cycles including stall cycles for unaligned accesses @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=unaligned + .include "raw4.ms" diff --git a/sim/testsuite/sim/cris/asm/raw17.ms b/sim/testsuite/sim/cris/asm/raw17.ms new file mode 100644 index 00000000000..07d18c597c8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw17.ms @@ -0,0 +1,29 @@ +; Checking read-after-write: different read-after-write combinations. +#mach: crisv32 +#output: Basic clock cycles, total @: 11\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 8\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d [$r1],$r2 + move.d [$r1],$r2 + clear.d [$r0] + move.d [$r1],$r2 + movem $r0,[$r1] + movem [$r1],$r0 + move $srp,[$r1] + move.d [$r1],$r0 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw2.ms b/sim/testsuite/sim/cris/asm/raw2.ms new file mode 100644 index 00000000000..cbbc47d3265 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw2.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-then-write unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d $r0,[$r1] + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw3.ms b/sim/testsuite/sim/cris/asm/raw3.ms new file mode 100644 index 00000000000..1c9a86b323a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw3.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: read-then-write unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d [$r0],$r2 + move.d $r0,[$r1] + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw4.ms b/sim/testsuite/sim/cris/asm/raw4.ms new file mode 100644 index 00000000000..75a77e9a836 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw4.ms @@ -0,0 +1,22 @@ +; Checking read-after-write: write-then-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw5.ms b/sim/testsuite/sim/cris/asm/raw5.ms new file mode 100644 index 00000000000..670e143b151 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw5.ms @@ -0,0 +1,23 @@ +; Checking read-after-write: write-then-nop-read 2 cycles. +#mach: crisv32 +#output: Basic clock cycles, total @: 5\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw6.ms b/sim/testsuite/sim/cris/asm/raw6.ms new file mode 100644 index 00000000000..d6e66364212 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw6.ms @@ -0,0 +1,24 @@ +; Checking read-after-write: write-then-nop-nop-read unaffected. +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + move.d $r1,[$r0] + nop + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw7.ms b/sim/testsuite/sim/cris/asm/raw7.ms new file mode 100644 index 00000000000..99da5f7b398 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw7.ms @@ -0,0 +1,25 @@ +; Checking read-after-write: movemwrite-then-read 2 cycles. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw8.ms b/sim/testsuite/sim/cris/asm/raw8.ms new file mode 100644 index 00000000000..8e42b9513b4 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw8.ms @@ -0,0 +1,26 @@ +; Checking read-after-write: movemwrite-then-nop-read 2 cycles. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 7\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 2\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/raw9.ms b/sim/testsuite/sim/cris/asm/raw9.ms new file mode 100644 index 00000000000..5c3881e9c35 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/raw9.ms @@ -0,0 +1,27 @@ +; Checking read-after-write: movemwrite-then-nop-nop-read unaffected. +#mach: crisv32 +#ld: --section-start=.text=0 +#output: Basic clock cycles, total @: 8\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 1\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "testutils.inc" + startnostack + .lcomm x,4*11 + .lcomm y,4 + move.d x,$r0 + move.d y,$r1 + nop + nop + movem $r10,[$r0] + nop + nop + move.d [$r1],$r2 + break 15 diff --git a/sim/testsuite/sim/cris/asm/ret.ms b/sim/testsuite/sim/cris/asm/ret.ms new file mode 100644 index 00000000000..578c5e1cba4 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/ret.ms @@ -0,0 +1,25 @@ +# mach: crisv3 crisv8 crisv10 +# output: 3\n + +# Test that ret works. + + .include "testutils.inc" + start +x: + moveq 0,r3 + jsr z +w: + quit +y: + addq 1,r3 + dumpr3 + quit + +z: + addq 1,r3 + move srp,r2 + add.d y-w,r2 + move r2,srp + ret + addq 1,r3 + quit diff --git a/sim/testsuite/sim/cris/asm/rfe.ms b/sim/testsuite/sim/cris/asm/rfe.ms new file mode 100644 index 00000000000..8d53778501f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/rfe.ms @@ -0,0 +1,47 @@ +# mach: crisv32 +# output: 4000c3af\n40000020\n40000080\n40000000\n + +; Check that RFE affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + +; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, +; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M: +; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + move 0x430efc00,ccs + + test_cc 0 0 0 0 + + rfe + test_cc 1 1 1 1 + move ccs,r3 + dumpr3 ; 0x4000c3af + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000020 + + rfe + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000080 + + or.w 0x100,r3 + move $r3,ccs + rfe + move ccs,r3 + dumpr3 ; 0x40000000 + + quit diff --git a/sim/testsuite/sim/cris/asm/rfg.ms b/sim/testsuite/sim/cris/asm/rfg.ms new file mode 100644 index 00000000000..f5439edd446 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/rfg.ms @@ -0,0 +1,9 @@ +# mach: crisv32 +# xerror: +# output: RFG isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + rfg + + quit diff --git a/sim/testsuite/sim/cris/asm/rfn.ms b/sim/testsuite/sim/cris/asm/rfn.ms new file mode 100644 index 00000000000..8f12530069a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/rfn.ms @@ -0,0 +1,53 @@ +# mach: crisv32 +# output: c008c1af\n40000220\n40000080\n40000000\n + +; Check that RFN affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + +; Clear S R P U I X N Z V C, set R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, +; clear S1 R2 P2 U2 N2 Z2 V2 C2, set S2 I2 X2 Q, clear M: +; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + move 0xa306fc00,ccs + + test_cc 0 0 0 0 + + rfn + test_cc 1 1 1 1 + move ccs,r3 + dumpr3 ; 0xc008c1af + + and.d 0x3fffffff,r3 + move r3,ccs + rfn + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000220 + + and.d 0x3fffffff,r3 + move r3,ccs + rfn + test_cc 0 0 0 0 + move ccs,r3 + dumpr3 ; 0x40000080 + + and.d 0x3fffffff,r3 + move r3,ccs + or.w 0x100,r3 + move r3,ccs + rfn + move ccs,r3 + dumpr3 ; 0x40000000 + + quit diff --git a/sim/testsuite/sim/cris/asm/sbfs.ms b/sim/testsuite/sim/cris/asm/sbfs.ms new file mode 100644 index 00000000000..1138e69249a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/sbfs.ms @@ -0,0 +1,7 @@ +# mach: crisv10 +# xerror: +# output: SBFS isn't implemented\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + sbfs [r10] diff --git a/sim/testsuite/sim/cris/asm/scc.ms b/sim/testsuite/sim/cris/asm/scc.ms new file mode 100644 index 00000000000..5925f8ab764 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/scc.ms @@ -0,0 +1,89 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n + + .include "testutils.inc" + + start + clearf nzvc + scc r3 + dumpr3 ; 1 + scs r3 + dumpr3 ; 0 + sne r3 + dumpr3 ; 1 + seq r3 + dumpr3 ; 0 + svc r3 + dumpr3 ; 1 + svs r3 + dumpr3 ; 0 + spl r3 + dumpr3 ; 1 + smi r3 + dumpr3 ; 0 + sls r3 + dumpr3 ; 0 + shi r3 + dumpr3 ; 1 + sge r3 + dumpr3 ; 1 + slt r3 + dumpr3 ; 0 + sgt r3 + dumpr3 ; 1 + sle r3 + dumpr3 ; 0 + sa r3 + dumpr3 ; 1 + setf nzvc + scc r3 + dumpr3 ; 0 + scs r3 + dumpr3 ; 1 + sne r3 + dumpr3 ; 0 + svc r3 + dumpr3 ; 0 + svs r3 + dumpr3 ; 1 + spl r3 + dumpr3 ; 0 + smi r3 + dumpr3 ; 1 + sls r3 + dumpr3 ; 1 + shi r3 + dumpr3 ; 0 + sge r3 + dumpr3 ; 1 + slt r3 + dumpr3 ; 0 + sgt r3 + dumpr3 ; 0 + sle r3 + dumpr3 ; 1 + sa r3 + dumpr3 ; 1 + clearf n + sge r3 + dumpr3 ; 0 + slt r3 + dumpr3 ; 1 + + .if ..asm.arch.cris.v32 + setf p + ssb r3 + .else + moveq 1,r3 + .endif + dumpr3 ; 1 + + .if ..asm.arch.cris.v32 + clearf p + ssb r3 + .else + moveq 0,r3 + .endif + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/sfe.ms b/sim/testsuite/sim/cris/asm/sfe.ms new file mode 100644 index 00000000000..b4b8e7c6b03 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/sfe.ms @@ -0,0 +1,51 @@ +# mach: crisv32 +# output: 4000c800\nc3221800\nc8606400\n48606400\n419d8260\n + +; Check that SFE affects CCS the right way. + + .include "testutils.inc" + start + +; Set SPC to 1 to disable single step exceptions when S flag is set. + move 1,spc + +; CCS: +; 31 24 23 16 15 8 7 0 +; +---+-----------+-------+-------+-----------+---+---------------+ +; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| +; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | +; +---+-----------+-------+-------+-----------+---+---------------+ + + move 0x40000000,ccs + setf ixv + sfe + move ccs,r3 + dumpr3 ; 0x4000c800 + or.d 0x80000000,r3 + move r3,ccs + + setf pzv + sfe + move ccs,r3 + dumpr3 ; 0xc3221800 + + setf xnc + sfe + move ccs,r3 + dumpr3 ; 0xc8606400 + +; Clear Q, so we don't get S and Q at the same time when we set S. + lslq 1,r3 + lsrq 1,r3 + move r3,ccs + move ccs,r3 + dumpr3 ; 0x48606400 + + or.w 0x300,r3 + move r3,ccs + setf ui + sfe + move ccs,r3 + dumpr3 ; 0x419d8260 + + quit diff --git a/sim/testsuite/sim/cris/asm/subc.ms b/sim/testsuite/sim/cris/asm/subc.ms new file mode 100644 index 00000000000..35d4e84ac0f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subc.ms @@ -0,0 +1,86 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + start + moveq -1,r3 + sub.d -2,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + sub.d 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.d -0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq -1,r3 + sub.d 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + sub.d -0x5432f789,r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + sub.w -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + sub.w 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + sub.w 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + sub.w 0x877,r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + sub.b -2,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffff01 + + moveq 2,r3 + sub.b 1,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xff,r3 + sub.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + sub.b 1,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + sub.b 0x77,r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649282,r3 + sub.b 0x82,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/sim/cris/asm/subm.ms b/sim/testsuite/sim/cris/asm/subm.ms new file mode 100644 index 00000000000..d84f34ada67 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subm.ms @@ -0,0 +1,96 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + .data +x: + .dword -2,1,-0xffff,1,-0x5432f789 + .word -2,1,1,0x877 + .byte -2,1,0x77 + .byte 0x22 + + start + moveq -1,r3 + move.d x,r5 + sub.d [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + sub.d [r5],r3 + test_cc 0 0 0 0 + addq 4,r5 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.d [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq -1,r3 + sub.d [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x78134452,r3 + sub.d [r5+],r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + sub.w [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + sub.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d 0x78134452,r3 + sub.w [r5+],r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + sub.b [r5],r3 + test_cc 0 0 0 0 + addq 1,r5 + dumpr3 ; ffffff01 + + moveq 2,r3 + sub.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xff,r3 + sub.b [r5],r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d 0xfeda49ff,r3 + sub.b [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d 0x78134452,r3 + sub.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649222,r3 + sub.b [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/sim/cris/asm/subq.ms b/sim/testsuite/sim/cris/asm/subq.ms new file mode 100644 index 00000000000..7b09267829e --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subq.ms @@ -0,0 +1,52 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 0\nffffffff\nfffffffe\nffff\nff\n56788f9\n56788d9\n567889a\n0\n7ffffffc\n + + .include "testutils.inc" + start + moveq 1,r3 + subq 1,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + subq 1,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffffff + + subq 1,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d 0x10000,r3 + subq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff + + move.d 0x100,r3 + subq 1,r3 + test_cc 0 0 0 0 + dumpr3 ; ff + + move.d 0x5678900,r3 + subq 7,r3 + test_cc 0 0 0 0 + dumpr3 ; 56788f9 + + subq 32,r3 + test_cc 0 0 0 0 + dumpr3 ; 56788d9 + + subq 63,r3 + test_cc 0 0 0 0 + dumpr3 ; 567889a + + move.d 34,r3 + subq 34,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x80000024,r3 + subq 40,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffffffc + + quit diff --git a/sim/testsuite/sim/cris/asm/subqpc.ms b/sim/testsuite/sim/cris/asm/subqpc.ms new file mode 100644 index 00000000000..dd4d2bfd94f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subqpc.ms @@ -0,0 +1,8 @@ +# mach: crisv3 crisv8 crisv10 +# xerror: +# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n + + .include "testutils.inc" + start + subq 31,pc + diff --git a/sim/testsuite/sim/cris/asm/subr.ms b/sim/testsuite/sim/cris/asm/subr.ms new file mode 100644 index 00000000000..ea77b77b913 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subr.ms @@ -0,0 +1,102 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n + + .include "testutils.inc" + start + moveq -1,r3 + moveq -2,r4 + sub.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + moveq 2,r3 + moveq 1,r4 + sub.d r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + move.d -0xffff,r4 + sub.d r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 1fffe + + moveq 1,r4 + moveq -1,r3 + sub.d r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffffffe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.d r4,r3 + test_cc 1 0 1 1 + dumpr3 ; cc463bdb + + moveq -1,r3 + moveq -2,r4 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffff0001 + + moveq 2,r3 + moveq 1,r4 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d 0xffff,r3 + move.d -0xffff,r4 + sub.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fffe + + move.d 0xfedaffff,r3 + move.d -0xfedaffff,r4 + sub.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fedafffe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78133bdb + + moveq -1,r3 + moveq -2,r4 + sub.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ffffff01 + + moveq 2,r3 + moveq 1,r4 + sub.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 1 + + move.d -0xff,r4 + move.d 0xff,r3 + sub.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; fe + + move.d -0xfeda49ff,r4 + move.d 0xfeda49ff,r3 + sub.b r4,r3 + test_cc 1 0 0 0 + dumpr3 ; feda49fe + + move.d -0x5432f789,r4 + move.d 0x78134452,r3 + sub.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; 781344db + + move.d 0x85649222,r3 + move.d 0x77445622,r4 + sub.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 85649200 + + quit diff --git a/sim/testsuite/sim/cris/asm/subxc.ms b/sim/testsuite/sim/cris/asm/subxc.ms new file mode 100644 index 00000000000..bd76adb0265 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subxc.ms @@ -0,0 +1,92 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + start + moveq 2,r3 + subs.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subs.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subu.b 0xff,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + move.d 0xffffffff,r4 + subu.w -1,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + subu.b -1,r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + subu.w -1,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + subs.b 0xff,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r3 + subs.w 0xffff,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + subs.b 0xff,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + moveq -1,r3 + subs.w 0xff,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + subs.w 0xffff,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + subu.b 0x89,r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x78134452,r3 + subs.b 0x89,r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x78134452,r3 + subu.w 0xf789,r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x78134452,r3 + subs.w 0xf789,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + subs.w 0x8002,r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + subu.w 0x764,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/sim/cris/asm/subxm.ms b/sim/testsuite/sim/cris/asm/subxm.ms new file mode 100644 index 00000000000..a4537d15a9a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subxm.ms @@ -0,0 +1,106 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + .data +x: + .byte 0xff + .word 0xffff + .word 0xff + .word 0xffff + .byte 0x89 + .word 0xf789 + .word 0x8002 + .word 0x764 + + start + moveq 2,r3 + move.d x,r5 + subs.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + subq 3,r5 + subu.b [r5+],r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + subu.w [r5+],r3 + test_cc 1 0 0 1 + subq 3,r5 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + subu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + subu.w [r5],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + subs.b [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r3 + subs.w [r5],r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + subs.b [r5],r3 + test_cc 0 1 0 0 + addq 3,r5 + dumpr3 ; 0 + + moveq -1,r3 + subs.w [r5+],r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + subs.w [r5+],r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x78134452,r3 + subu.b [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x78134452,r3 + subs.b [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x78134452,r3 + subu.w [r5],r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x78134452,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + subs.w [r5+],r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + subu.w [r5+],r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/sim/cris/asm/subxr.ms b/sim/testsuite/sim/cris/asm/subxr.ms new file mode 100644 index 00000000000..e894596dc6d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/subxr.ms @@ -0,0 +1,108 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n + + .include "testutils.inc" + start + moveq 2,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + move.d 0xffff,r4 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 3 + + moveq 2,r3 + move.d 0xffff,r4 + subu.b r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffffff03 + + moveq 2,r3 + move.d 0xffffffff,r4 + subu.w r4,r3 + test_cc 1 0 0 1 + dumpr3 ; ffff0003 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + subu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; ff00 + + move.d 0xffff,r3 + move.d 0xffffffff,r4 + subu.w r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0xffff,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + move.d 0xffff,r4 + move.d r4,r3 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 10000 + + moveq -1,r3 + move.d 0xff,r4 + subs.b r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + moveq -1,r3 + move.d 0xff,r4 + subs.w r4,r3 + test_cc 1 0 0 0 + dumpr3 ; ffffff00 + + moveq -1,r3 + move.d 0xffff,r4 + subs.w r4,r3 + test_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subu.b r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 781343c9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subs.b r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 781344c9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subu.w r4,r3 + test_cc 0 0 0 0 + dumpr3 ; 78124cc9 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; 78134cc9 + + move.d 0x4452,r3 + move.d 0x78568002,r4 + subs.w r4,r3 + test_cc 0 0 0 1 + dumpr3 ; c450 + + move.d 0x80000032,r3 + move.d 0xffff0764,r4 + subu.w r4,r3 + test_cc 0 0 1 0 + dumpr3 ; 7ffff8ce + + quit diff --git a/sim/testsuite/sim/cris/asm/swap.ms b/sim/testsuite/sim/cris/asm/swap.ms new file mode 100644 index 00000000000..de7ca495a7c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/swap.ms @@ -0,0 +1,87 @@ +# mach: crisv8 crisv10 crisv32 +# output: 1ec8224a\n13785244\nc81e4a22\n44527813\n224a1ec8\n52441378\n4a22c81e\n87ecbbad\ne137ddb5\nec87adbb\n37e1b5dd\nbbad87ec\nddb5e137\nadbbec87\nb5dd37e1\n0\n + + .include "testutils.inc" + start + move.d 0x78134452,r4 + move.d r4,r3 + swapr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 1ec8224a + + move.d r4,r3 + swapb r3 + test_move_cc 0 0 0 0 + dumpr3 ; 13785244 + + move.d r4,r3 + swapbr r3 + test_move_cc 1 0 0 0 + dumpr3 ; c81e4a22 + + move.d r4,r3 + swapw r3 + test_move_cc 0 0 0 0 + dumpr3 ; 44527813 + + move.d r4,r3 + swapwr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 224a1ec8 + + move.d r4,r3 + swapwb r3 + test_move_cc 0 0 0 0 + dumpr3 ; 52441378 + + move.d r4,r3 + swapwbr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 4a22c81e + + move.d r4,r3 + swapn r3 + test_move_cc 1 0 0 0 + dumpr3 ; 87ecbbad + + move.d r4,r3 + swapnr r3 + test_move_cc 1 0 0 0 + dumpr3 ; e137ddb5 + + move.d r4,r3 + swapnb r3 + test_move_cc 1 0 0 0 + dumpr3 ; ec87adbb + + move.d r4,r3 + swapnbr r3 + test_move_cc 0 0 0 0 + dumpr3 ; 37e1b5dd + + move.d r4,r3 + swapnw r3 + test_move_cc 1 0 0 0 + dumpr3 ; bbad87ec + + move.d r4,r3 + swapnwr r3 + test_move_cc 1 0 0 0 + dumpr3 ; ddb5e137 + + move.d r4,r3 + swapnwb r3 + test_move_cc 1 0 0 0 + dumpr3 ; adbbec87 + + move.d r4,r3 + swapnwbr r3 + test_move_cc 1 0 0 0 + dumpr3 ; b5dd37e1 + + moveq -1,r3 + swapnwbr r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/tb.ms b/sim/testsuite/sim/cris/asm/tb.ms new file mode 100644 index 00000000000..eb6eaf9afbd --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tb.ms @@ -0,0 +1,72 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 54\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 18\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check branch penalties. It is assumed that the taken-counters +; in the bimodal branch-predictors start at 0, meaning two taken +; branches are required for a branch to be predicted as taken +; for each counter, from reset. None of these branches go +; to the end of a cache-line and none map to the same counter. + + .include "testutils.inc" + startnostack + ba 0f ; No penalty: always-taken condition not "predicted". + nop + nop +0: + setf c + bcs 0f ; Penalty 2 cycles. + nop + + nop +0: + clearf c + bcc 0f ; Penalty 2 cycles, though branch is a nop. + moveq 4,r0 ; Execute 5 times: + +0: + move.d r0,r0 + bne 0b ; Mispredicted 3 out of 5 times: penalty 3*2 cycles. + subq 1,r0 + +0: + beq 0f ; Not taken; no penalty. + nop + + nop +0: + +; (Almost) same insns, but with 16-bit bCC insns. + + ba 0f ; No penalty: always-taken condition not "predicted". + nop + .space 520 +0: + setf c + bcs 0f ; Penalty 2 cycles. + nop + + .space 520 +0: + moveq 4,r0 ; Execute 5 times: +0: + ba 1f + move.d r0,r0 ; Mispredicted 3 out of 5 times: + .space 520 +1: + bne 0b ; Penalty 3*2 cycles. + subq 1,r0 + + beq 0f ; Not taken; no penalty. + nop +0: + break 15 diff --git a/sim/testsuite/sim/cris/asm/test.ms b/sim/testsuite/sim/cris/asm/test.ms new file mode 100644 index 00000000000..93c4f591f40 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/test.ms @@ -0,0 +1,80 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 1\n + + .include "testutils.inc" + .data +x: + .dword 0,2,-1,0x80000000,0x5432f789 + .word 0,2,-1,0xffff,0xf789 + .byte 0,2,0xff,0x89 + + start + clearf nzvc + moveq -1,r3 + move.d x,r5 + setf vc + test.d [r5+] + test_cc 0 1 0 0 + + setf vc + test.d [r5] + test_cc 0 0 0 0 + + addq 4,r5 + + setf vc + test.d [r5+] + test_cc 1 0 0 0 + + setf vc + test.d [r5+] + test_cc 1 0 0 0 + + setf vc + test.d [r5+] + test_cc 0 0 0 0 + + setf vc + test.w [r5+] + test_cc 0 1 0 0 + + setf vc + test.w [r5] + test_cc 0 0 0 0 + + addq 2,r5 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.w [r5+] + test_cc 1 0 0 0 + + setf vc + test.b [r5] + test_cc 0 1 0 0 + + addq 1,r5 + + setf vc + test.b [r5+] + test_cc 0 0 0 0 + + setf vc + test.b [r5+] + test_cc 1 0 0 0 + + setf vc + test.b [r5] + test_cc 1 0 0 0 + + moveq 1,r3 + dumpr3 + + quit diff --git a/sim/testsuite/sim/cris/asm/testutils.inc b/sim/testsuite/sim/cris/asm/testutils.inc new file mode 100644 index 00000000000..06e63c598b6 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/testutils.inc @@ -0,0 +1,353 @@ +; Copied from fr30 and modified. +; r9, r11-r13 are used as tmps, consider them call clobbered by these macros. +; +; Do not use the macro counter \@ in macros, there's a bug in +; gas 2.9.1 when it is also a line-separator. +; + + ; Don't require the $-prefix on registers. + .syntax no_register_prefix + + .macro startnostack + .data + .space 64,0 ; Simple stack +stackhi: +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + break 11 + .global _start +_start: + .endm + + .macro start + startnostack + move.d stackhi,sp + .endm + +; Exit with return code + .macro exit rc + move.d \rc,r10 + moveq 1,r9 ; == __NR_exit + break 13 + break 15 + .endm + +; Pass the test case + .macro pass + moveq 5,r12 + move.d passmsg,r11 + move.d 1,r10 + moveq 4,r9 ; == __NR_write + break 13 + exit 0 + .endm + +; Fail the testcase + .macro fail +; moveq 5,r12 +; move.d failmsg,r11 +; move.d 1,r10 +; moveq 4,r1 +; break 13 +; exit 1 + break 15 + .endm + + .macro quit + break 15 + .endm + + .macro dumpr3 + break 14 + .endm + +; Load an immediate value into a general register +; TODO: use minimal sized insn + .macro mvi_h_gr val reg + move.d \val,\reg + .endm + +; Load an immediate value into a dedicated register + .macro mvi_h_dr val reg + move.d \val,r9 + move.d r9,\reg + .endm + +; Load a general register into another general register + .macro mvr_h_gr src targ + move.d \src,\targ + .endm + +; Store an immediate into a word in memory + .macro mvi_h_mem val addr + mvi_h_gr \val r11 + mvr_h_mem r11,\addr + .endm + +; Store a register into a word in memory + .macro mvr_h_mem reg addr + move.d \reg,@\addr + .endm + +; Store the current ps on the stack + .macro save_ps + .if ..asm.arch.cris.v32 + move ccs,acr ; Push will do a "subq" first. + push acr + .else + push dccr + .endif + .endm + +; Load a word value from memory + .macro ldmem_h_gr addr reg + move.d @\addr,\reg + .endm + +; Add 2 general registers + .macro add_h_gr reg1 reg2 + add.d \reg1,\reg2 + .endm + +; Increment a register by and immediate + .macro inci_h_gr inc reg + mvi_h_gr \inc,r11 + add.d r11,\reg + .endm + +; Test the value of an immediate against a general register + .macro test_h_gr val reg + cmp.d \val,\reg + beq 9f + nop + fail +9: + .endm + +; compare two general registers + .macro testr_h_gr reg1 reg2 + cmp.d \reg1,\reg2 + beq 9f + fail +9: + .endm + +; Test the value of an immediate against a dedicated register + .macro test_h_dr val reg + move.d \reg,r12 + test_h_gr \val r12 + .endm + +; Test the value of an general register against a dedicated register + .macro testr_h_dr gr dr + move.d \dr,r12 + testr_h_gr \gr r12 + .endm + +; Compare an immediate with word in memory + .macro test_h_mem val addr + ldmem_h_gr \addr r12 + test_h_gr \val r12 + .endm + +; Compare a general register with word in memory + .macro testr_h_mem reg addr + ldmem_h_gr \addr r12 + testr_h_gr \reg r12 + .endm + +; Set the condition codes +; The lower bits of the mask *are* nzvc, so we don't +; have to do anything strange. + .macro set_cc mask + move.w \mask,r13 + .if ..asm.arch.cris.v32 + move r13,ccs + .else + move r13,ccr + .endif + .endm + +; Set the stack mode +; .macro set_s_user +; orccr 0x20 +; .endm +; +; .macro set_s_system +; andccr 0x1f +; .endm +; +;; Test the stack mode +; .macro test_s_user +; mvr_h_gr ps,r9 +; mvi_h_gr 0x20,r11 +; and r11,r9 +; test_h_gr 0x20,r9 +; .endm +; +; .macro test_s_system +; mvr_h_gr ps,r9 +; mvi_h_gr 0x20,r11 +; and r11,r9 +; test_h_gr 0x0,r9 +; .endm + +; Set the interrupt bit +; ??? Do they mean "enable interrupts" or "disable interrupts"? +; Assuming enable here. + .macro set_i val + .if (\val == 1) + ei + .else + di + .endif + .endm + +; Test the stack mode +; .macro test_i val +; mvr_h_gr ps,r9 +; mvi_h_gr 0x10,r11 +; and r11,r9 +; .if (\val == 1) +; test_h_gr 0x10,r9 +; .else +; test_h_gr 0x0,r9 +; .endif +; .endm +; +;; Set the ilm +; .macro set_ilm val +; stilm \val +; .endm +; +;; Test the ilm +; .macro test_ilm val +; mvr_h_gr ps,r9 +; mvi_h_gr 0x1f0000,r11 +; and r11,r9 +; mvi_h_gr \val,r12 +; mvi_h_gr 0x1f,r11 +; and r11,r12 +; lsl 15,r12 +; lsl 1,r12 +; testr_h_gr r9,r12 +; .endm +; +; Test the condition codes + .macro test_cc N Z V C + .if \N + bpl 9f + nop + .else + bmi 9f + nop + .endif + .if \Z + bne 9f + nop + .else + beq 9f + nop + .endif + .if \V + bvc 9f + nop + .else + bvs 9f + nop + .endif + .if \C + bcc 9f + nop + .else + bcs 9f + nop + .endif + ba 8f + nop +9: + fail +8: + .endm + + .macro test_move_cc N Z V C + .if ..asm.arch.cris.v32 + clearf vc + .endif + .endm + +; Set the division bits +; .macro set_dbits val +; mvr_h_gr ps,r12 +; mvi_h_gr 0xfffff8ff,r11 +; and r11,r12 +; mvi_h_gr \val,r9 +; mvi_h_gr 3,r11 +; and r11,r9 +; lsl 9,r9 +; or r9,r12 +; mvr_h_gr r12,ps +; .endm +; +;; Test the division bits +; .macro test_dbits val +; mvr_h_gr ps,r9 +; lsr 9,r9 +; mvi_h_gr 3,r11 +; and r11,r9 +; test_h_gr \val,r9 +; .endm +; +; Save the return pointer + .macro save_rp + push srp + .ENDM + +; restore the return pointer + .macro restore_rp + pop srp + .endm + +; Ensure branch taken + .macro take_branch opcode + \opcode 9f + nop + fail +9: + .endm + + .macro take_branch_d opcode val + \opcode 9f + nop + move.d \val,r9 + fail +9: + test_h_gr \val,r9 + .endm + +; Ensure branch not taken + .macro no_branch opcode + \opcode 9f + nop + ba 8f + nop +9: + fail +8: + .endm + + .macro no_branch_d opcode val + \opcode 9f + move.d \val,r9 + nop + ba 8f + nop +9: + fail +8: + test_h_gr \val,r9 + .endm + diff --git a/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms b/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms new file mode 100644 index 00000000000..dee0b2913e4 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms @@ -0,0 +1,55 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 37\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 6\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that we correctly account for that a "jas N,Pn", +; "jasc N,Pn", "bas N,Pn" and "basc N,Pn" sets the specific +; special register and causes a pipeline hazard. The amount +; of nops below is a bit inflated, in an attempt to make +; errors more discernible. For special registers, we just +; check SRP. + + .include "testutils.inc" + startnostack + move.d 0f,$r0 + jsr 0f + nop + nop + nop + jsrc 0f + nop + .dword -1 + nop + nop + jsr $r0 + nop + nop + nop + jsrc $r0 + nop + .dword -1 + nop + nop + bsr 0f + nop + nop + nop + bsrc 0f + nop + .dword -1 + nop + nop + break 15 + +0: + ret ; 1 cycle penalty. + nop diff --git a/sim/testsuite/sim/cris/asm/tjmpsrv32.ms b/sim/testsuite/sim/cris/asm/tjmpsrv32.ms new file mode 100644 index 00000000000..1781c4f0613 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tjmpsrv32.ms @@ -0,0 +1,50 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 17\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 5\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that "ret"-type insns get the right number of penalty +; cycles for the special register source. + + .include "testutils.inc" + startnostack + move.d 1f,$r1 + move.d 0f,$r0 + move $r0,$mof + jump $mof ; 2 cycles penalty. + nop + +0: + move [$r1],$srp + nop + ret ; 1 cycle penalty. + nop + + break 15 + +0: + move 2f,$nrp + nop + nop + jump $nrp ; no penalty. + nop + + break 15 + +2: + move 3f,$srp ; 2 cycles penalty. + ret + nop + +3: + break 15 +1: + .dword 0b diff --git a/sim/testsuite/sim/cris/asm/tjsrcv10.ms b/sim/testsuite/sim/cris/asm/tjsrcv10.ms new file mode 100644 index 00000000000..3bc694648b8 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tjsrcv10.ms @@ -0,0 +1,29 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that the 4-byte-skip doesn't make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + nop + move.d 0f,r5 + jsrc r5 + nop + .dword -1 +0: + jsrc 1f + nop + .dword -2 +1: + break 15 diff --git a/sim/testsuite/sim/cris/asm/tjsrcv32.ms b/sim/testsuite/sim/cris/asm/tjsrcv32.ms new file mode 100644 index 00000000000..a777f01bda6 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tjsrcv32.ms @@ -0,0 +1,13 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 2\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmemv10.ms b/sim/testsuite/sim/cris/asm/tmemv10.ms new file mode 100644 index 00000000000..40b32a9206d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmemv10.ms @@ -0,0 +1,27 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 8\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that the memory indirection doesn't make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + move.d [r5],r4 + move.d [r5+],r3 + move.d [r5],r2 + break 15 + nop + .p2align 2 +0: + .dword 1,2,3 diff --git a/sim/testsuite/sim/cris/asm/tmemv32.ms b/sim/testsuite/sim/cris/asm/tmemv32.ms new file mode 100644 index 00000000000..81ce21162a9 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmemv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 4\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmulv10.ms b/sim/testsuite/sim/cris/asm/tmulv10.ms new file mode 100644 index 00000000000..3d855a2796b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmulv10.ms @@ -0,0 +1,26 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 9\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that multiplications do not make the simulator barf. +; Nothing deeper. + + .include "testutils.inc" + startnostack + moveq 1,r3 + moveq 2,r1 + moveq 1,r0 + muls.d r0,r1 + muls.d r0,r3 + mulu.d r1,r3 + break 15 + nop diff --git a/sim/testsuite/sim/cris/asm/tmulv32.ms b/sim/testsuite/sim/cris/asm/tmulv32.ms new file mode 100644 index 00000000000..3326054e59d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmulv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 6\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 2\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmvm1.ms b/sim/testsuite/sim/cris/asm/tmvm1.ms new file mode 100644 index 00000000000..c1c925d0dd1 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvm1.ms @@ -0,0 +1,53 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 18\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 6\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to register followed by register write dword +; to one of the registers is logged as needing two stall cycles, +; regardless of size. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + moveq 0,r8 + moveq 0,r9 + + movem [r5],r4 + move.d r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.w r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.b r8,r1 + addq 1,r1 ; 2 cycles. + + movem [r5],r4 + move.b r8,r1 + addq 1,r9 + + movem [r5],r4 + move.d r8,r1 + addq 1,r8 + + break 15 + + .data + .p2align 5 +0: + .dword 0b + .dword 0b + .dword 0b + .dword 0b + .dword 0b diff --git a/sim/testsuite/sim/cris/asm/tmvm2.ms b/sim/testsuite/sim/cris/asm/tmvm2.ms new file mode 100644 index 00000000000..176d3ccfe6a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvm2.ms @@ -0,0 +1,351 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: *\n +#output: Memory source stall cycles: 82\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 6\n +#output: Movem destination stall cycles: 880\n +#output: Movem address stall cycles: 4\n +#output: Multiplication source stall cycles: 18\n +#output: Jump source stall cycles: 6\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "testutils.inc" + +; Macros for testing correctness of movem destination stall +; cycles for various insn types. Beware: macro parameters can +; be comma or space-delimited. There are problems (i.e. bugs) +; with using space-delimited operands and operands with +; non-alphanumeric characters, like "[]-." so use comma for +; them. Lots of trouble passing empty parameters and parameters +; with comma. Ugh. FIXME: Report bugs, fix bugs, fix other +; shortcomings, fix that darn old macro-parameter-in-string. + +; Helper macro. Unfortunately I find no cleaner way to unify +; one and two-operand cases, the main problem being the comma +; operand delimiter clashing with macro operand delimiter. + .macro t_S_x_y S insn x y=none + movem [r7],r6 + .ifc \y,none + .ifc \S,none + \insn \x + .else + \insn\S \x + .endif + .else + .ifc \S,none + \insn \x,\y + .else + \insn\S \x,\y + .endif + .endif + nop + nop + nop + .endm + +; An insn-type that has a single register operand. The register +; may or may not be a source register for the insn. + .macro t_r insn + t_S_x_y none,\insn,r3 + t_S_x_y none,\insn,r8 + .endm + +; An insn-type that jumps to the destination of the register. + .macro t_r_j insn + move.d 0f,r7 + move.d 1f,r8 + move.d r8,r9 + nop + nop + nop + .section ".rodata" + .p2align 5 +0: + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .dword 1f + .previous + t_r \insn +1: + .endm + +; An insn-type that has a size-modifier and two register +; operands. + .macro t_xr_r S insn + t_S_x_y \S \insn r3 r8 + t_S_x_y \S \insn r8 r3 + move.d r3,r9 + t_S_x_y \S \insn r4 r3 + t_S_x_y \S \insn r8 r9 + .endm + +; An insn-type that has two register operands. + .macro t_r_r insn + t_xr_r none \insn + .endm + +; An t_r_rx insn with a byte or word-size modifier. + .macro t_wbr_r insn + t_xr_r .b,\insn + t_xr_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbr_r insn + t_xr_r .d,\insn + t_wbr_r \insn + .endm + +; An insn-type that has a size-modifier, a constant and a +; register operand. + .macro t_xc_r S insn + t_S_x_y \S \insn 24 r3 + move.d r3,r9 + t_S_x_y \S \insn 24 r8 + .endm + +; An insn-type that has a constant and a register operand. + .macro t_c_r insn + t_xc_r none \insn + .endm + +; An t_c_r insn with a byte or word-size modifier. + .macro t_wbc_r insn + t_xc_r .b,\insn + t_xc_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbc_r insn + t_xc_r .d,\insn + t_wbc_r \insn + .endm + +; An insn-type that has size-modifier, a memory operand and a +; register operand. + .macro t_xm_r S insn + move.d 9b,r8 + t_S_x_y \S,\insn,[r4],r3 + move.d r3,r9 + t_S_x_y \S,\insn,[r8],r5 + move.d r5,r9 + t_S_x_y \S,\insn,[r3],r9 + t_S_x_y \S,\insn,[r8],r9 + .endm + +; Ditto, to memory. + .macro t_xr_m S insn + move.d 9b,r8 + t_S_x_y \S,\insn,r3,[r4] + t_S_x_y \S,\insn,r8,[r3] + t_S_x_y \S,\insn,r3,[r8] + t_S_x_y \S,\insn,r9,[r8] + .endm + +; An insn-type that has a memory operand and a register operand. + .macro t_m_r insn + t_xm_r none \insn + .endm + +; An t_m_r insn with a byte or word-size modifier. + .macro t_wbm_r insn + t_xm_r .b,\insn + t_xm_r .w,\insn + .endm + +; Ditto with a dword-size modifier. + .macro t_dwbm_r insn + t_xm_r .d,\insn + t_wbm_r \insn + .endm + +; Insn types of the regular type (r, c, m, size d w b). + .macro t_dwb insn + t_dwbr_r \insn + t_dwbc_r \insn + t_dwbm_r \insn + .endm + +; Similar, sizes w b. + .macro t_wb insn + t_wbr_r \insn + t_wbc_r \insn + t_wbm_r \insn + .endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + startnostack + +; Initialize registers so they don't contain unknowns. + + move.d 9f,r7 + move.d r7,r8 + moveq 0,r9 + +; Movem source area. Register contents must be valid +; addresses, aligned on a cache boundary. + .section ".rodata" + .p2align 5 +9: + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .dword 9b + .previous + +; The actual tests. The numbers in the comments specify the +; number of movem destination stall cycles. Some of them may be +; filed as memory source address stalls, multiplication source +; stalls or jump source stalls, duly marked so. + + t_r_r abs ; 3+3 + + t_dwb add ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + + t_r_r addc ; (3+3+3) + t_c_r addc ; 3 + t_m_r addc ; (3+3+3) (2 mem src) + + t_dwb move ; (3+3)+(3+3+3)*2+3*2+(3+3+3)*3 (6 mem src) + t_xr_m .b move ; 3+3+3 (2 mem src) + t_xr_m .w move ; 3+3+3 (2 mem src) + t_xr_m .d move ; 3+3+3 (2 mem src) + + t_S_x_y none addi r3.b r8 ; 3 + t_S_x_y none addi r8.w r3 ; 3 + t_S_x_y none addi r4.d r3 ; 3 + t_S_x_y none addi r8.w r9 + + ; Addo has three-operand syntax, so we have to expand (a useful + ; subset of) "t_dwb". + t_S_x_y none addi r3.b "r8,acr" ; 3 + t_S_x_y none addi r8.w "r3,acr" ; 3 + t_S_x_y none addi r4.d "r3,acr" ; 3 + t_S_x_y none addi r8.w "r9,acr" + + t_S_x_y .b addo 42 "r8,acr" + t_S_x_y .w addo 4200 "r3,acr" ; 3 + t_S_x_y .d addo 420000 "r3,acr" ; 3 + + move.d 9b,r8 + t_S_x_y .d,addo,[r4],"r3,acr" ; 3 (1 mem src) + t_S_x_y .b,addo,[r3],"r8,acr" ; 3 (1 mem src) + t_S_x_y .w,addo,[r8],"r3,acr" ; 3 + t_S_x_y .w,addo,[r8],"r9,acr" + + ; Similar for addoq. + t_S_x_y none addoq 42 "r8,acr" + t_S_x_y none addoq 42 "r3,acr" ; 3 + + t_c_r addq ; 3 + + t_wb adds ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + t_wb addu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + + t_dwb and ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r andq ; 3 + + t_dwbr_r asr ; (3+3+3)*3 + t_c_r asrq ; 3 + + t_dwbr_r bound ; (3+3+3)*3 + t_dwbc_r bound ; 3*3 + + t_r_r btst ; (3+3+3) + t_c_r btstq ; 3 + + t_dwb cmp ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r cmpq ; 3 + + t_wbc_r cmps ; 3*2 + t_wbc_r cmpu ; 3*2 + t_wbm_r cmps ; (3+3+3)*2 (4 mem src) + t_wbm_r cmpu ; (3+3+3)*2 (4 mem src) + + t_r_r dstep ; (3+3+3) + + ; FIXME: idxd, fidxi, ftagd, ftagi when supported. + + t_r_j jsr ; 3 (2 jump src) + t_r_j jump ; 3 (2 jump src) + + t_c_r lapc.d + +; The "quick operand" must be in range [. to .+15*2] so we can't +; use t_c_r. + t_S_x_y none lapcq .+4 r3 + t_S_x_y none lapcq .+4 r8 + + t_dwbr_r lsl ; (3+3+3)*3 + t_c_r lslq ; 3 + + t_dwbr_r lsr ; (3+3+3)*3 + t_c_r lsrq ; 3 + + t_r_r lz ; 3+3 + + t_S_x_y none mcp srp r3 ; 3 + t_S_x_y none mcp srp r8 + + t_c_r moveq + + t_S_x_y none move srp r8 + t_S_x_y none move srp r3 + t_S_x_y none move r8 srp + t_S_x_y none move r3 srp ; 3 + +; FIXME: move supreg,Rd and move Rs,supreg when supported. + + t_wb movs ; (3+3)*2+0+(3+3)*2 (4 mem src) + t_wb movu ; (3+3)*2+0+(3+3)*2 (4 mem src) + + t_dwbr_r muls ; (3+3+3)*3 (9 mul src) + t_dwbr_r mulu ; (3+3+3)*3 (9 mul src) + + t_dwbr_r neg ; (3+3)*3 + + t_r not ; 3 cycles. + + t_dwb or ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r orq ; 3 + + t_r seq + + t_dwb sub ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) + t_c_r subq ; 3 + + t_wb subs ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + t_wb subu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) + + t_r swapw ; 3 cycles. + t_r swapnwbr ; 3 cycles. + + t_r_j jsrc ; 3 (2 jump src) + + t_r_r xor ; (3+3+3) + + move.d 9b,r7 + nop + nop + nop + t_xm_r none movem ; (3+3) (2 mem src, 1+1 movem addr) + ; As implied by the comment, all movem destination penalty + ; cycles (but one) are accounted for as memory source address + ; and movem source penalties. There are also two movem address + ; cache-line straddle penalties. + t_xr_m none movem ; (3+3+2+2) (2 mem, 6 movem src, +2 movem addr) + + break 15 diff --git a/sim/testsuite/sim/cris/asm/tmvmrv10.ms b/sim/testsuite/sim/cris/asm/tmvmrv10.ms new file mode 100644 index 00000000000..66b9b1fe983 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvmrv10.ms @@ -0,0 +1,50 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 45\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to register basically looks ok cycle-wise. +; Nothing deep. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + moveq 0,r8 + moveq 0,r9 + +; Adapted from crisv32 movem-to-memory penalty examples many +; revisions ago. + + movem [r5],r4 + test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest). + movem [r5],r4 + subq 1,r8 + test.d [r3] ; 2 cycle penalty on v32. + movem [r5],r4 + subq 1,r1 ; 3 cycle penalty on v32. + movem [r5],r4 + add.d r8,r9 + subq 1,r1 ; 2 cycle penalty on v32. + movem [r5],r4 + add.d r8,r9 + subq 1, r9 + subq 1, r1 ; 1 cycle penalty on v32. + break 15 + + .data + .p2align 5 +0: + .dword 0b + .dword 0b + .dword 0b + .dword 0b + .dword 0b + diff --git a/sim/testsuite/sim/cris/asm/tmvmrv32.ms b/sim/testsuite/sim/cris/asm/tmvmrv32.ms new file mode 100644 index 00000000000..0501747e84b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvmrv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 17\n +#output: Memory source stall cycles: 1\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 10\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmvmrv10.ms" diff --git a/sim/testsuite/sim/cris/asm/tmvrmv10.ms b/sim/testsuite/sim/cris/asm/tmvrmv10.ms new file mode 100644 index 00000000000..c782997530d --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvrmv10.ms @@ -0,0 +1,40 @@ +#mach: crisv10 +#output: Basic clock cycles, total @: 31\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 0\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + +; Check that movem to memory basically looks ok cycle-wise. +; Nothing deep. + + .include "testutils.inc" + startnostack + move.d 0f,r4 + moveq 0,r0 + moveq 1,r3 + moveq 2,r1 + moveq 1,r2 + movem r3,[r4] ; 2 cycles penalty for v32 + movem r3,[r4] ; 0 cycles penalty for v32 + moveq 1,r3 + nop + movem r3,[r4] ; 1 cycle penalty for v32 + moveq 1,r3 + nop + nop + movem r3,[r4] ; 0 cycles penalty for v32 + break 15 + + .data +0: + .dword 0 + .dword 0 + .dword 0 + .dword 0 diff --git a/sim/testsuite/sim/cris/asm/tmvrmv32.ms b/sim/testsuite/sim/cris/asm/tmvrmv32.ms new file mode 100644 index 00000000000..339ab20b18b --- /dev/null +++ b/sim/testsuite/sim/cris/asm/tmvrmv32.ms @@ -0,0 +1,14 @@ +#mach: crisv32 +#output: Basic clock cycles, total @: 14\n +#output: Memory source stall cycles: 0\n +#output: Memory read-after-write stall cycles: 0\n +#output: Movem source stall cycles: 3\n +#output: Movem destination stall cycles: 0\n +#output: Movem address stall cycles: 0\n +#output: Multiplication source stall cycles: 0\n +#output: Jump source stall cycles: 0\n +#output: Branch misprediction stall cycles: 0\n +#output: Jump target stall cycles: 0\n +#sim: --cris-cycles=basic + + .include "tmvrmv10.ms" diff --git a/sim/testsuite/sim/cris/asm/user.ms b/sim/testsuite/sim/cris/asm/user.ms new file mode 100644 index 00000000000..f6115bbeec3 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/user.ms @@ -0,0 +1,75 @@ +# mach: crisv32 +# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n + +; Check for protected operations being NOP in user mode, for the +; parts implemented in this simulator. + + .include "testutils.inc" + start + move 0,ccs + move 0,usp + move 0,pid + move 0,srs + move 0,ebp + move 0,spc + setf u + +; Flag settings, besides what's tested in rfn.ms, rfe.ms and +; sfe.ms. + setf i + move ccs,r3 + dumpr3 ; 0x40 + + clearf u + move ccs,r3 + dumpr3 ; 0x40 + + move 0xc0000300,ccs + move ccs,r3 + dumpr3 ; 0x140 + +; R14==USP + move.d 0xabadefb0,r14 + nop + nop + nop + move usp,r3 + dumpr3 ; 0xabadefb0 + move 0x6543789c,usp + nop + nop + nop + move.d r14,r3 + dumpr3 ; 0x6543789c + +; We can't go back to kernel mode, so we can't check that R14 in +; kernel mode wasn't affected. + +; Moves to protected special registers. + .macro testsr reg,val=-1 + move \val,\reg + ; Registers shorter than dword will not affect the rest of the + ; general register when copied using a move insn. + clear.d r3 +; Three cycles are needed between move to protected register and +; read from it, to avoid reading undefined contents due to +; incomplete forwarding. + nop + nop + move \reg,r3 + dumpr3 + moveq \val,r3 + move r3,\reg + clear.d r3 + nop + nop + move \reg,r3 + dumpr3 + .endm + + testsr pid ; 0 0 + testsr srs,3 ; 0 0 + testsr ebp ; 0 0 + testsr spc ; 0 0 + + quit diff --git a/sim/testsuite/sim/cris/asm/x0-v10.ms b/sim/testsuite/sim/cris/asm/x0-v10.ms new file mode 100644 index 00000000000..4ead73e28ea --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x0-v10.ms @@ -0,0 +1,7 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[cde][0-9a-f][0-9a-f] ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[cde][0-9a-f][0-9a-f] ixnzvc 1\n +#sim: --cris-trace=basic + + .include "break.ms" diff --git a/sim/testsuite/sim/cris/asm/x0-v32.ms b/sim/testsuite/sim/cris/asm/x0-v32.ms new file mode 100644 index 00000000000..a707f6d41b6 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x0-v32.ms @@ -0,0 +1,7 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[cde][0-9a-f][0-9a-f] ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[cde][0-9a-f][0-9a-f] ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "break.ms" diff --git a/sim/testsuite/sim/cris/asm/x1-v10.ms b/sim/testsuite/sim/cris/asm/x1-v10.ms new file mode 100644 index 00000000000..e1a87c1053c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x1-v10.ms @@ -0,0 +1,8 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 3\n +#sim: --cris-trace=basic + + .include "movect10.ms" diff --git a/sim/testsuite/sim/cris/asm/x1-v32.ms b/sim/testsuite/sim/cris/asm/x1-v32.ms new file mode 100644 index 00000000000..d37cfddc525 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x1-v32.ms @@ -0,0 +1,8 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 1 0\n +#sim: --cris-trace=basic + + .include "movect10.ms" diff --git a/sim/testsuite/sim/cris/asm/x10-v10.ms b/sim/testsuite/sim/cris/asm/x10-v10.ms new file mode 100644 index 00000000000..4b7e4aa4904 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x10-v10.ms @@ -0,0 +1,21 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "add.d x,pc" gets 3 cycles. + + .include "testutils.inc" + startnostack + nop + nop + add.d 1f-0f,$pc +0: + nop +1: + nop + break 15 diff --git a/sim/testsuite/sim/cris/asm/x2-v10.ms b/sim/testsuite/sim/cris/asm/x2-v10.ms new file mode 100644 index 00000000000..e2d5bbf6679 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x2-v10.ms @@ -0,0 +1,59 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n +#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n +#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n +#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n +#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n +#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n +#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n + .include "tb.ms" diff --git a/sim/testsuite/sim/cris/asm/x2-v32.ms b/sim/testsuite/sim/cris/asm/x2-v32.ms new file mode 100644 index 00000000000..0fdfcfdeb10 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x2-v32.ms @@ -0,0 +1,59 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n +#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n +#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n +#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n + .include "tb.ms" diff --git a/sim/testsuite/sim/cris/asm/x3-v10.ms b/sim/testsuite/sim/cris/asm/x3-v10.ms new file mode 100644 index 00000000000..113e18db491 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x3-v10.ms @@ -0,0 +1,10 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#sim: --cris-trace=basic + + .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x3-v32.ms b/sim/testsuite/sim/cris/asm/x3-v32.ms new file mode 100644 index 00000000000..93a74366a6f --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x3-v32.ms @@ -0,0 +1,10 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "tjsrcv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x4-v32.ms b/sim/testsuite/sim/cris/asm/x4-v32.ms new file mode 100644 index 00000000000..056c05c304c --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x4-v32.ms @@ -0,0 +1,23 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 10 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 12 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 14 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 16 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 18 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 1e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 24 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 26 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 28 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 2a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 2e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 34 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 36 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 38 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#sim: --cris-trace=basic + + .include "tjmpsrv32.ms" diff --git a/sim/testsuite/sim/cris/asm/x5-v10.ms b/sim/testsuite/sim/cris/asm/x5-v10.ms new file mode 100644 index 00000000000..ec5023e84ba --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x5-v10.ms @@ -0,0 +1,9 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n + .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x5-v32.ms b/sim/testsuite/sim/cris/asm/x5-v32.ms new file mode 100644 index 00000000000..62b3fcad913 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x5-v32.ms @@ -0,0 +1,9 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + .include "tmemv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x6-v10.ms b/sim/testsuite/sim/cris/asm/x6-v10.ms new file mode 100644 index 00000000000..910daf87138 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x6-v10.ms @@ -0,0 +1,11 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n + .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x6-v32.ms b/sim/testsuite/sim/cris/asm/x6-v32.ms new file mode 100644 index 00000000000..19c5ada8af6 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x6-v32.ms @@ -0,0 +1,11 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n +#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + .include "tmulv10.ms" diff --git a/sim/testsuite/sim/cris/asm/x7-v10.ms b/sim/testsuite/sim/cris/asm/x7-v10.ms new file mode 100644 index 00000000000..f465143f504 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x7-v10.ms @@ -0,0 +1,29 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 5\n +#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n +#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n +#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 5\n +#sim: --cris-trace=basic + +; Check that prefix+insn are traced as one. + + .include "testutils.inc" + startnostack + nop + move.d [0f],r3 + nop + moveq 0,r4 + move.d [r3+r4.b],r5 + move.d [r3+4],r5 + bdap.d 0,r3 + move.d [r3],r5 + break 15 + .p2align 2 +0: + .dword 0b + .dword 0b diff --git a/sim/testsuite/sim/cris/asm/x7-v32.ms b/sim/testsuite/sim/cris/asm/x7-v32.ms new file mode 100644 index 00000000000..ea98ef0548a --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x7-v32.ms @@ -0,0 +1,19 @@ +#mach: crisv32 +#ld: --section-start=.text=0 +#sim: --cris-trace=basic +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n +#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvc 1 aa424243\n +#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 55212121\n +#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 1\n +#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n + +; Check that trace with changing ACR works. + + .include "testutils.inc" + startnostack + move.d 0xaa424243,$acr + lsrq 1,$acr + moveq 1,$acr + clear.d $acr + break 15 + nop diff --git a/sim/testsuite/sim/cris/asm/x8-v10.ms b/sim/testsuite/sim/cris/asm/x8-v10.ms new file mode 100644 index 00000000000..672cc2110ff --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x8-v10.ms @@ -0,0 +1,20 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 8 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: c 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n +#output: e 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "jump [rN]" gets 2 cycles. + + .include "testutils.inc" + startnostack + move.d 0f,r5 + jump [r5] + break 15 +1: + nop + break 15 +0: + .dword 1b diff --git a/sim/testsuite/sim/cris/asm/x9-v10.ms b/sim/testsuite/sim/cris/asm/x9-v10.ms new file mode 100644 index 00000000000..68472beed67 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/x9-v10.ms @@ -0,0 +1,23 @@ +#mach: crisv10 +#ld: --section-start=.text=0 +#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n +#output: 4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n +#output: 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 4\n +#output: 12 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n +#sim: --cris-trace=basic + +; Check that "adds.w [$pc+$r9.w],$pc" gets 4 cycles. + + .include "testutils.inc" + startnostack + moveq 1,r9 + adds.w [$pc+$r9.w],$pc +0: + .word 1f-0b + .word 2f-0b + .word 1f-0b +1: + break 15 +2: + nop + break 15 diff --git a/sim/testsuite/sim/cris/asm/xor.ms b/sim/testsuite/sim/cris/asm/xor.ms new file mode 100644 index 00000000000..2095dea8b82 --- /dev/null +++ b/sim/testsuite/sim/cris/asm/xor.ms @@ -0,0 +1,47 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: 3\n3\nff0\n0\n2c21b3db\n0\nffffffff\n + + .include "testutils.inc" + start + moveq 1,r3 + moveq 2,r4 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + moveq 2,r3 + moveq 1,r4 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 3 + + move.d 0xff0f,r4 + move.d 0xf0ff,r3 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; ff0 + + moveq -1,r4 + move.d r4,r3 + xor r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x5432f789,r4 + move.d 0x78134452,r3 + xor r4,r3 + test_move_cc 0 0 0 0 + dumpr3 ; 2c21b3db + + moveq 0,r4 + moveq 0,r3 + xor r4,r3 + test_move_cc 0 1 0 0 + dumpr3 ; 0 + + move.d 0x7fffffff,r3 + move.d 0x80000000,r4 + xor r4,r3 + test_move_cc 1 0 0 0 + dumpr3 ; ffffffff + quit diff --git a/sim/testsuite/sim/cris/c/append1.c b/sim/testsuite/sim/cris/c/append1.c new file mode 100644 index 00000000000..0acd59d2827 --- /dev/null +++ b/sim/testsuite/sim/cris/c/append1.c @@ -0,0 +1,51 @@ +/* Check regression of a bug uncovered by the libio tFile test (old + libstdc++, pre-gcc-3.x era), where appending to a file doesn't work. + The default open-flags-mapping does not match Linux/CRIS, so a + specific mapping is necessary. */ + +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "a+"); + if (f == NULL + || fwrite (tsttxt2, 1, strlen (tsttxt2), f) != strlen (tsttxt2) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != sizeof (buf) - 1 + || strncmp (buf, tsttxt1, strlen (tsttxt1)) != 0 + || strncmp (buf + strlen (tsttxt1), tsttxt2, strlen (tsttxt2)) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/c.exp b/sim/testsuite/sim/cris/c/c.exp new file mode 100644 index 00000000000..c76fc773112 --- /dev/null +++ b/sim/testsuite/sim/cris/c/c.exp @@ -0,0 +1,211 @@ +# Copyright (C) 2005 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +# Miscellaneous CRIS simulator testcases testing syscall sequences. + +if ![istarget cris*-*-*] { + return +} + +set CFLAGS_FOR_TARGET "-O2" +if [istarget cris-*-*] { + set mach "crisv10" +} { + set mach "crisv32" +} + +# Using target_compile, since it is less noisy, +if { [target_compile $srcdir/$subdir/hello.c compilercheck.x \ + "executable" "" ] == "" } { + set has_cc 1 +} { + verbose -log "Can't execute C compiler" + set has_cc 0 +} + +# Like istarget, except take a list of targets as a string. +proc anytarget { targets } { + set targetlist [split $targets] + set argc [llength $targetlist] + for { set i 0 } { $i < $argc } { incr i } { + if [istarget [lindex $targetlist $i]] { + return 1 + } + } + return 0 +} + +foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] { + if ![runtest_file_p $runtests $src] { + continue + } + set testname "[file tail $src]" + + set opt_array [slurp_options $src] + if { $opt_array == -1 } { + unresolved $testname + return + } + + # And again, to simplify specifying tests. + if ![runtest_file_p $runtests $src] { + continue + } + + # Note absence of CC in results, but don't make a big fuss over it. + if { $has_cc == 0 } { + untested $testname + continue + } + + # Clear default options + set opts(cc) "" + set opts(sim) "" + set opts(output) "" + set opts(progoptions) "" + set opts(timeout) "" + set opts(mach) "" + set opts(xerror) "no" + set opts(dest) "$testname.x" + set opts(simenv) "" + set opts(kfail) "" + set opts(xfail) "" + set opts(target) "" + set opts(notarget) "" + + # Clear any machine specific options specified in a previous test case + if [info exists opts(sim,$mach)] { + unset opts(sim,$mach) + } + + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + if ![info exists opts($opt_name)] { + perror "unknown option $opt_name in file $src" + unresolved $testname + return + } + + # Replace specific substitutions: + # @exedir@ is where the test-program is located. + regsub -all "@exedir@" $opt_val "[pwd]" opt_val + # @srcdir@ is where the source of the test-program is located. + regsub -all "@srcdir@" $opt_val "$srcdir/$subdir" opt_val + + # Multiple of these options concatenate, they don't override. + if { $opt_name == "output" || $opt_name == "progoptions" } { + set opt_val "$opts($opt_name)$opt_val" + } + + # Similar with "xfail", "kfail", "target" and "notarget", but + # arguments are space-separated. + if { $opt_name == "xfail" || $opt_name == "kfail" \ + || $opt_name == "target" || $opt_name == "notarget" } { + if { $opts($opt_name) != "" } { + set opt_val "$opts($opt_name) $opt_val" + } + } + + foreach m $opt_machs { + set opts($opt_name,$m) $opt_val + } + if { "$opt_machs" == "" } { + set opts($opt_name) $opt_val + } + } + + if { $opts(output) == "" } { + if { "$opts(xerror)" == "no" } { + set opts(output) "pass\n" + } else { + set opts(output) "fail\n" + } + } + + if { $opts(target) != "" && ![anytarget $opts(target)] } { + continue + } + + if { $opts(notarget) != "" && [anytarget $opts(notarget)] } { + continue + } + + # If no machine specific options, default to the general version. + if ![info exists opts(sim,$mach)] { + set opts(sim,$mach) $opts(sim) + } + + # Change \n sequences to newline chars. + regsub -all "\\\\n" $opts(output) "\n" opts(output) + + verbose -log "Compiling $src with $opts(cc)" + + set dest "$opts(dest)" + if { [sim_compile $src $dest "executable" "$opts(cc)" ] != "" } { + unresolved $testname + continue + } + + verbose -log "Simulating $src with $opts(sim,$mach)" + + # Time to setup xfailures and kfailures. + if { "$opts(xfail)" != "" } { + verbose -log "xfail: $opts(xfail)" + # Using eval to make $opts(xfail) appear as individual + # arguments. + eval setup_xfail $opts(xfail) + } + if { "$opts(kfail)" != "" } { + verbose -log "kfail: $opts(kfail)" + eval setup_kfail $opts(kfail) + } + + set result [sim_run $dest "$opts(sim,$mach)" "$opts(progoptions)" \ + "" "$opts(simenv)"] + set status [lindex $result 0] + set output [lindex $result 1] + + if { "$status" == "pass" } { + if { "$opts(xerror)" == "no" } { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } else { + verbose -log "`pass' return code when expecting failure" 3 + fail "$mach $testname (execution)" + } + } elseif { "$status" == "fail" } { + if { "$opts(xerror)" == "no" } { + fail "$mach $testname (execution)" + } else { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } + } else { + $status "$mach $testname" + } +} diff --git a/sim/testsuite/sim/cris/c/clone1.c b/sim/testsuite/sim/cris/c/clone1.c new file mode 100644 index 00000000000..163b18647a8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/clone1.c @@ -0,0 +1,90 @@ +/* +#notarget: cris*-*-elf +#output: got: a\nthen: bc\nexit: 0\n +*/ + +/* This is a very limited subset of what ex1.c does; we just check that + thread creation (clone syscall) and pipe writes and reads work. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + char *s = arg; + if (write (pip[1], s+2, 1) != 1) abort (); + if (write (pip[1], s+1, 1) != 1) abort (); + if (write (pip[1], s, 1) != 1) abort (); + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st; + long stack[16384]; + char buf[10] = {0}; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "cba"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if ((retcode = read (pip[0], buf, 1)) != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + printf ("got: %c\n", buf[0]); + retcode = read (pip[0], buf, 2); + if (retcode == 1) + { + retcode = read (pip[0], buf+1, 1); + if (retcode != 1) + { + fprintf (stderr, "Bad read 1.5: %d\n", retcode); + abort (); + } + retcode = 2; + } + if (retcode != 2) + { + fprintf (stderr, "Bad read 2: %d\n", retcode); + abort (); + } + + printf ("then: %s\n", buf); + retcode = wait4 (-1, &st, WNOHANG | __WCLONE, NULL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d %x\n", retcode, st); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/clone2.c b/sim/testsuite/sim/cris/c/clone2.c new file mode 100644 index 00000000000..e433a778b34 --- /dev/null +++ b/sim/testsuite/sim/cris/c/clone2.c @@ -0,0 +1,6 @@ +/* Make sure the thread system trivially works with trace output. +#notarget: cris*-*-elf +#sim: --cris-trace=basic --trace-file=@exedir@/clone2.tmp +#output: got: a\nthen: bc\nexit: 0\n +*/ +#include "clone1.c" diff --git a/sim/testsuite/sim/cris/c/clone3.c b/sim/testsuite/sim/cris/c/clone3.c new file mode 100644 index 00000000000..0a97484adac --- /dev/null +++ b/sim/testsuite/sim/cris/c/clone3.c @@ -0,0 +1,45 @@ +/* Check that exiting from a parent thread does not kill the child. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 50; i++) + if (sched_yield ()) + abort (); + + printf ("pass\n"); + return 0; +} + +int +main (void) +{ + int pid; + long stack[16384]; + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/clone4.c b/sim/testsuite/sim/cris/c/clone4.c new file mode 100644 index 00000000000..81489ddc419 --- /dev/null +++ b/sim/testsuite/sim/cris/c/clone4.c @@ -0,0 +1,61 @@ +/* Check that TRT happens when we reach the #threads implementation limit. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 500; i++) + if (sched_yield ()) + abort (); + + return 0; +} + +int +main (void) +{ + int pid; + int i; + int stacksize = 16384; + + for (i = 0; i < 1000; i++) + { + char *stack = malloc (stacksize); + if (stack == NULL) + abort (); + + pid = clone (process, (char *) stack + stacksize - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + /* FIXME: Read sysconf instead of magic number. */ + if (i < 60) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if (errno == EAGAIN) + { + printf ("pass\n"); + exit (0); + } + } + } + + abort (); +} diff --git a/sim/testsuite/sim/cris/c/clone5.c b/sim/testsuite/sim/cris/c/clone5.c new file mode 100644 index 00000000000..b642a2f1a35 --- /dev/null +++ b/sim/testsuite/sim/cris/c/clone5.c @@ -0,0 +1,32 @@ +/* Check that unimplemented clone syscalls get the right treatment. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented clone syscall * +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + return 0; +} + +int +main (void) +{ + int retcode; + long stack[16384]; + + clone (process, (char *) stack + sizeof (stack) - 64, 0, "cba"); + printf ("xyzzy\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/ex1.c b/sim/testsuite/sim/cris/c/ex1.c new file mode 100644 index 00000000000..2447319f71a --- /dev/null +++ b/sim/testsuite/sim/cris/c/ex1.c @@ -0,0 +1,54 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: Starting process a\naaaaaaaaStarting process b\nababbbbbbbbb + + The output will change depending on the exact syscall sequence per + thread, so will change with glibc versions. Prepare to modify; use + the latest glibc. + + This file is from glibc/linuxthreads, with the difference that the + number is 10, not 10000. */ + +/* Creates two threads, one printing 10000 "a"s, the other printing + 10000 "b"s. + Illustrates: thread creation, thread joining. */ + +#include +#include +#include +#include "pthread.h" + +static void * +process (void *arg) +{ + int i; + fprintf (stderr, "Starting process %s\n", (char *) arg); + for (i = 0; i < 10; i++) + { + write (1, (char *) arg, 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + fprintf (stderr, "create a failed %d\n", retcode); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + fprintf (stderr, "create b failed %d\n", retcode); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + fprintf (stderr, "join a failed %d\n", retcode); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + fprintf (stderr, "join b failed %d\n", retcode); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/fcntl1.c b/sim/testsuite/sim/cris/c/fcntl1.c new file mode 100644 index 00000000000..e180841645a --- /dev/null +++ b/sim/testsuite/sim/cris/c/fcntl1.c @@ -0,0 +1,16 @@ +/* Check that we get the expected message for unsupported fcntl calls. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented fcntl* +#output: program stopped with signal 4.\n +*/ +#include +#include +#include + +int main (void) +{ + fcntl (1, 42); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/fdopen1.c b/sim/testsuite/sim/cris/c/fdopen1.c new file mode 100644 index 00000000000..cdfe19af7d7 --- /dev/null +++ b/sim/testsuite/sim/cris/c/fdopen1.c @@ -0,0 +1,54 @@ +/* Check that the syscalls implementing fdopen work trivially. */ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + char buf[sizeof (tsttxt1)] = ""; + + fd = open (fname, O_WRONLY|O_TRUNC|O_CREAT, S_IRWXU); + if (fd <= 0) + perr ("open-w"); + + f = fdopen (fd, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + + if (fclose (f) != 0) + perr ("fclose"); + + fd = open (fname, O_RDONLY); + if (fd <= 0) + perr ("open-r"); + + f = fdopen (fd, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) + || strcmp (buf, tsttxt1) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/fdopen2.c b/sim/testsuite/sim/cris/c/fdopen2.c new file mode 100644 index 00000000000..6a59f367a34 --- /dev/null +++ b/sim/testsuite/sim/cris/c/fdopen2.c @@ -0,0 +1,52 @@ +/* Check that the syscalls implementing fdopen work trivially. +#output: This is the first line of this test.\npass\n +*/ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first line of this test.\n"; + char buf[sizeof (tsttxt1)] = ""; + + /* Write a line to stdout. */ + f = fdopen (1, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + +#if 0 + /* Unfortunately we can't get < /dev/null to the simulator with + reasonable test-framework surgery. */ + + /* Try to read from stdin. Expect EOF. */ + f = fdopen (0, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != 0 + || feof (f) == 0 + || ferror (f) != 0) + { + printf ("fail\n"); + exit (1); + } +#endif + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/freopen1.c b/sim/testsuite/sim/cris/c/freopen1.c new file mode 100644 index 00000000000..eeb6079fdb5 --- /dev/null +++ b/sim/testsuite/sim/cris/c/freopen1.c @@ -0,0 +1,52 @@ +/* Check that basic freopen functionality works. +#xfail: *-*-* + Currently doesn't work, because syscall.c:cb_syscall case + CB_SYS_write intercepts writes to fd 1 and 2. */ + +#include +#include +#include + +int +main (void) +{ + FILE *old_stderr; + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct freopen etc.\n"; + char buf[sizeof tsttxt] = ""; + + /* Like the freopen call in flex. */ + old_stderr = freopen (fname, "w+", stderr); + if (old_stderr == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) + || fclose (stderr) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/ftruncate1.c b/sim/testsuite/sim/cris/c/ftruncate1.c new file mode 100644 index 00000000000..46b8756705c --- /dev/null +++ b/sim/testsuite/sim/cris/c/ftruncate1.c @@ -0,0 +1,52 @@ +/* Check that the ftruncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("open or fwrite"); + + if (fflush (f) != 0) + perr ("fflush"); + + if (ftruncate (fileno (f), strlen(tsttxt1) - 20) != 0) + perr ("ftruncate"); + + if (fclose (f) != 0) + perr ("fclose"); + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 20 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 20) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/ftruncate2.c b/sim/testsuite/sim/cris/c/ftruncate2.c new file mode 100644 index 00000000000..f1ef18c6aa6 --- /dev/null +++ b/sim/testsuite/sim/cris/c/ftruncate2.c @@ -0,0 +1,39 @@ +/* +#notarget: cris*-*-elf +*/ + +/* Check that we get a proper error indication if trying ftruncate on a + fd that is a pipe descriptor. */ + +#include +#include +#include +#include +int main (void) +{ + int pip[2]; + + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (ftruncate (pip[0], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 1"); + abort (); + } + + errno = 0; + + if (ftruncate (pip[1], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 2"); + abort (); + } + + printf ("pass\n"); + + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/getcwd1.c b/sim/testsuite/sim/cris/c/getcwd1.c new file mode 100644 index 00000000000..3838916143a --- /dev/null +++ b/sim/testsuite/sim/cris/c/getcwd1.c @@ -0,0 +1,18 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (getcwd ((void *) -1, 4096) != NULL + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/gettod.c b/sim/testsuite/sim/cris/c/gettod.c new file mode 100644 index 00000000000..18a000cd45c --- /dev/null +++ b/sim/testsuite/sim/cris/c/gettod.c @@ -0,0 +1,27 @@ +/* Basic time functionality test. */ +#include +#include +#include +#include +int +main (void) +{ + struct timeval t_m = {0, 0}; + time_t t; + + if ((t = time (NULL)) == (time_t) -1 + || gettimeofday (&t_m, NULL) != 0 + || t_m.tv_sec == 0 + + /* We assume there will be no delay between the time and + gettimeofday calls above, but allow a timer-tick to make the + seconds increase by one. */ + || (t != t_m.tv_sec && t+1 != t_m.tv_sec)) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/hello.c b/sim/testsuite/sim/cris/c/hello.c new file mode 100644 index 00000000000..fb403ba9961 --- /dev/null +++ b/sim/testsuite/sim/cris/c/hello.c @@ -0,0 +1,7 @@ +#include +#include +int main () +{ + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/kill1.c b/sim/testsuite/sim/cris/c/kill1.c new file mode 100644 index 00000000000..e5c53a0daf8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/kill1.c @@ -0,0 +1,30 @@ +/* Basic kill functionality test; fail killing init. Don't run as root. */ +#include +#include +#include +#include +#include +int +main (void) +{ + if (kill (1, SIGTERM) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + if (kill (1, SIGABRT) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/kill2.c b/sim/testsuite/sim/cris/c/kill2.c new file mode 100644 index 00000000000..183091cf664 --- /dev/null +++ b/sim/testsuite/sim/cris/c/kill2.c @@ -0,0 +1,16 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +int +main (void) +{ + kill (getpid (), SIGABRT); + printf ("undead\n"); + exit (1); +} diff --git a/sim/testsuite/sim/cris/c/kill3.c b/sim/testsuite/sim/cris/c/kill3.c new file mode 100644 index 00000000000..b70f3d324dc --- /dev/null +++ b/sim/testsuite/sim/cris/c/kill3.c @@ -0,0 +1,16 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +int +main (void) +{ + abort (); + printf ("undead\n"); + exit (1); +} diff --git a/sim/testsuite/sim/cris/c/mapbrk.c b/sim/testsuite/sim/cris/c/mapbrk.c new file mode 100644 index 00000000000..1aff7622bc2 --- /dev/null +++ b/sim/testsuite/sim/cris/c/mapbrk.c @@ -0,0 +1,39 @@ +#include +#include + +/* Basic sanity check that syscalls to implement malloc (brk, mmap2, + munmap) are trivially functional. */ + +int main () +{ + void *p1, *p2, *p3, *p4, *p5, *p6; + + if ((p1 = malloc (8100)) == NULL + || (p2 = malloc (16300)) == NULL + || (p3 = malloc (4000)) == NULL + || (p4 = malloc (500)) == NULL + || (p5 = malloc (1023*1024)) == NULL + || (p6 = malloc (8191*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + free (p3); + free (p4); + free (p5); + free (p6); + + p1 = malloc (64000); + if (p1 == NULL) + { + printf ("fail\n"); + exit (1); + } + free (p1); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/mmap1.c b/sim/testsuite/sim/cris/c/mmap1.c new file mode 100644 index 00000000000..b803f0c431e --- /dev/null +++ b/sim/testsuite/sim/cris/c/mmap1.c @@ -0,0 +1,48 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + + a = mmap (NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/mmap2.c b/sim/testsuite/sim/cris/c/mmap2.c new file mode 100644 index 00000000000..35139a0ed9a --- /dev/null +++ b/sim/testsuite/sim/cris/c/mmap2.c @@ -0,0 +1,48 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + + a = mmap (NULL, size, PROT_READ, MAP_SHARED, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/mmap3.c b/sim/testsuite/sim/cris/c/mmap3.c new file mode 100644 index 00000000000..34401fa0c90 --- /dev/null +++ b/sim/testsuite/sim/cris/c/mmap3.c @@ -0,0 +1,33 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + volatile unsigned char *a; + + /* Check that we can map a non-multiple of a page and still get a full page. */ + a = mmap (NULL, 0x4c, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (a == NULL || a == (unsigned char *) -1) + abort (); + + a[0] = 0xbe; + a[8191] = 0xef; + memset ((char *) a + 1, 0, 8190); + + if (a[0] != 0xbe || a[8191] != 0xef) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/mprotect1.c b/sim/testsuite/sim/cris/c/mprotect1.c new file mode 100644 index 00000000000..ef249ec691f --- /dev/null +++ b/sim/testsuite/sim/cris/c/mprotect1.c @@ -0,0 +1,16 @@ +/* Check unimplemented-output for mprotect call. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented mprotect call (0x0, 0x2001, 0x4)\n +#output: program stopped with signal 4.\n + */ +#include +#include +#include + +int main (int argc, char *argv[]) +{ + mprotect (0, 8193, PROT_EXEC); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/mremap.c b/sim/testsuite/sim/cris/c/mremap.c new file mode 100644 index 00000000000..e78a8a43f7a --- /dev/null +++ b/sim/testsuite/sim/cris/c/mremap.c @@ -0,0 +1,31 @@ +#include +#include + +/* Sanity check that system calls for realloc works. Also tests a few + more cases for mmap2 and munmap. */ + +int main () +{ + void *p1, *p2; + + if ((p1 = malloc (8100)) == NULL + || (p1 = realloc (p1, 16300)) == NULL + || (p1 = realloc (p1, 4000)) == NULL + || (p1 = realloc (p1, 500)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL + || (p2 = malloc (1023*1024)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/openpf1.c b/sim/testsuite/sim/cris/c/openpf1.c new file mode 100644 index 00000000000..1d71e0bddb0 --- /dev/null +++ b/sim/testsuite/sim/cris/c/openpf1.c @@ -0,0 +1,38 @@ +/* Check that --sysroot is applied to open(2). +#sim: --sysroot=@exedir@ + + We assume, with EXE being the name of the executable: + - The simulator executes with cwd the same directory where the executable + is located (so argv[0] contains a plain filename without directory + components). + - There's no /EXE on the host file system. */ + +#include +#include +#include +#include +int main (int argc, char *argv[]) +{ + char *fnam = argv[0]; + FILE *f; + if (argv[0][0] != '/') + { + fnam = malloc (strlen (argv[0]) + 2); + if (fnam == NULL) + abort (); + strcpy (fnam, "/"); + strcat (fnam, argv[0]); + } + + f = fopen (fnam, "rb"); + if (f == NULL) + abort (); + close (f); + + /* Cover another execution path. */ + if (fopen ("/nonexistent", "rb") != NULL + || errno != ENOENT) + abort (); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/openpf2.c b/sim/testsuite/sim/cris/c/openpf2.c new file mode 100644 index 00000000000..fe7c265a272 --- /dev/null +++ b/sim/testsuite/sim/cris/c/openpf2.c @@ -0,0 +1,16 @@ +/* Check that the simulator has chdir:ed to the --sysroot argument +#sim: --sysroot=@srcdir@ + (or that --sysroot is applied to relative file paths). */ + +#include +#include +#include +int main (int argc, char *argv[]) +{ + FILE *f = fopen ("openpf2.c", "rb"); + if (f == NULL) + abort (); + close (f); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/openpf3.c b/sim/testsuite/sim/cris/c/openpf3.c new file mode 100644 index 00000000000..557adee92de --- /dev/null +++ b/sim/testsuite/sim/cris/c/openpf3.c @@ -0,0 +1,49 @@ +/* Basic file operations (rename, unlink); once without sysroot. We + also test that the simulator has chdir:ed to PREFIX, when defined. */ + +#include +#include +#include +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + FILE *f; + struct stat buf; + + unlink (PREFIX "testfoo2.tmp"); + + f = fopen ("testfoo1.tmp", "w"); + if (f == NULL) + err ("open"); + fclose (f); + + if (rename (PREFIX "testfoo1.tmp", PREFIX "testfoo2.tmp") != 0) + err ("rename"); + + if (stat (PREFIX "testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 1"); + + if (stat ("testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 2"); + + if (unlink (PREFIX "testfoo2.tmp") != 0) + err ("unlink"); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/openpf4.c b/sim/testsuite/sim/cris/c/openpf4.c new file mode 100644 index 00000000000..d3fdcfe2f90 --- /dev/null +++ b/sim/testsuite/sim/cris/c/openpf4.c @@ -0,0 +1,5 @@ +/* Basic file operations, now *with* sysroot. +#sim: --sysroot=@exedir@ +*/ +#define PREFIX "/" +#include "openpf3.c" diff --git a/sim/testsuite/sim/cris/c/openpf5.c b/sim/testsuite/sim/cris/c/openpf5.c new file mode 100644 index 00000000000..1f86ea283d4 --- /dev/null +++ b/sim/testsuite/sim/cris/c/openpf5.c @@ -0,0 +1,56 @@ +/* Check that TRT happens when error on too many opened files. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + char *fn = malloc (strlen (argv[0]) + 2); + if (fn == NULL) + abort (); + strcpy (fn, "/"); + strcat (fn, argv[0]); + + for (i = 0; i < filemax + 1; i++) + { + if (open (fn, O_RDONLY) < 0) + { + /* Shouldn't happen too early. */ + if (i < filemax - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("open"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/pipe1.c b/sim/testsuite/sim/cris/c/pipe1.c new file mode 100644 index 00000000000..ddc4285e02f --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe1.c @@ -0,0 +1,47 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + if (filemax < 10) + abort (); + + /* Check that pipes don't leak file descriptors. */ + for (i = 0; i < filemax * 10; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (close (pip[0]) != 0 || close (pip[1]) != 0) + { + perror ("close"); + abort (); + } + } + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/pipe2.c b/sim/testsuite/sim/cris/c/pipe2.c new file mode 100644 index 00000000000..ccb97f82d4e --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe2.c @@ -0,0 +1,124 @@ +/* Check that closing a pipe with a nonempty buffer works. +#notarget: cris*-*-elf +#output: got: a\nexit: 0\n +*/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + char *buf = malloc (pipemax * 100); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + /* The first write should go straight through. */ + if (write (pip[1], buf, 1) != 1) + abort (); + + *buf = s[1]; + + /* The second write should only successful for at most the PIPE_MAX + part, but no error. */ + ret = write (pip[1], buf, pipemax * 10); + if (ret != 0 && ret != pipemax - 1 && ret != pipemax) + { + fprintf (stderr, "ret: %d\n", ret); + fflush (0); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + /* We need to turn this off because we don't want (to have to model) a + SIGPIPE resulting from the close. */ + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + abort (); + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/pipe3.c b/sim/testsuite/sim/cris/c/pipe3.c new file mode 100644 index 00000000000..bf08a38e1f0 --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe3.c @@ -0,0 +1,48 @@ +/* Check that TRT happens when error on pipe call. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + /* Check that TRT happens when error on pipe call. */ + for (i = 0; i < filemax + 1; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + /* Shouldn't happen too early. */ + if (i < filemax / 2 - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("pipe"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/pipe4.c b/sim/testsuite/sim/cris/c/pipe4.c new file mode 100644 index 00000000000..1cb309f9dc8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe4.c @@ -0,0 +1,66 @@ +/* Check that TRT happens for pipe corner cases. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + char c; + int pipemax; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing to wrong end of pipe. */ + if (write (pip[0], "argh", 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + /* Reading from wrong end of pipe. */ + if (read (pip[1], &c, 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + if (close (pip[0]) != 0) + err ("close"); + + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + err ("signal"); + + /* Writing to pipe with closed read end. */ + if (write (pip[1], "argh", 1) != -1 + || errno != EPIPE) + err ("write closed"); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/pipe5.c b/sim/testsuite/sim/cris/c/pipe5.c new file mode 100644 index 00000000000..abf1c9fcd99 --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe5.c @@ -0,0 +1,59 @@ +/* Check that TRT happens for pipe corner cases (for our definition of TRT). +#notarget: cris*-*-elf +#xerror: +#output: Terminating simulation due to writing pipe * from one single thread\n +#output: program stopped with signal 4.\n +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + int pipemax; + char *buf; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing an inordinate amount to the pipe. */ + buf = calloc (100 * pipemax, 1); + if (buf == NULL) + err ("calloc"); + + /* The following doesn't trig on host; writing more than PIPE_MAX to a + pipe with no reader makes the program hang. Neither does it trig + on target: we don't want to emulate the "hanging" (which would + happen with *any* amount written to a pipe with no reader if we'd + support it - but we don't). Better to abort the simulation with a + suitable message. */ + if (write (pip[1], buf, 100 * pipemax) != -1 + || errno != EFBIG) + err ("write mucho"); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/pipe6.c b/sim/testsuite/sim/cris/c/pipe6.c new file mode 100644 index 00000000000..a8830cc3e69 --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe6.c @@ -0,0 +1,111 @@ +/* Check that writing an inordinate amount of data works (somewhat). +#notarget: cris*-*-elf +#output: got: a\nexit: 0\n + This test-case will *not* work on host (or for real): the first + pipemax+1 bytes will be successfully written. It's just for + exercising a rare execution path. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + char *buf = calloc (pipemax * 100, 1); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + ret = write (pip[1], buf, pipemax * 100); + if (ret != -1 || errno != EFBIG) + { + perror ("write"); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/pipe7.c b/sim/testsuite/sim/cris/c/pipe7.c new file mode 100644 index 00000000000..552ddb8e1e8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/pipe7.c @@ -0,0 +1,21 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (pipe (NULL) != -1 + || errno != EFAULT) + { + perror ("pipe"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/readlink1.c b/sim/testsuite/sim/cris/c/readlink1.c new file mode 100644 index 00000000000..1898e8eceb5 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink1.c @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + /* This depends on the test-setup, but it's unlikely that the program + is passed as a symlink, so supposedly safe. */ + if (readlink(argv[0], buf, sizeof (buf)) != -1 || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/readlink10.c b/sim/testsuite/sim/cris/c/readlink10.c new file mode 100644 index 00000000000..21744083edd --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink10.c @@ -0,0 +1,18 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (readlink("/proc/42/exe", NULL, 4096) != -1 + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/readlink2.c b/sim/testsuite/sim/cris/c/readlink2.c new file mode 100644 index 00000000000..5a0d8785caf --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink2.c @@ -0,0 +1,73 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + char buf2[1024]; + + /* This is a special feature handled in the simulator. The "42" + should be formed from getpid () if this was a real program. */ + if (readlink ("/proc/42/exe", buf, sizeof (buf)) < 0) + abort (); + + /* Don't use an abort in the following; it might cause the printf to + not make it all the way to output and make debugging more + difficult. */ + + /* We assume the program is called with no path, so we might need to + prepend it. */ + if (getcwd (buf2, sizeof (buf2)) != buf2) + { + perror ("getcwd"); + exit (1); + } + + if (argv[0][0] == '/') + { +#ifdef SYSROOTED + if (strchr (argv[0] + 1, '/') != NULL) + { + printf ("%s != %s\n", argv[0], strrchr (argv[0] + 1, '/')); + exit (1); + } +#endif + if (strcmp (argv[0], buf) != 0) + { + printf ("%s != %s\n", buf, argv[0]); + exit (1); + } + } + else if (argv[0][0] != '.') + { + if (buf2[strlen (buf2) - 1] != '/') + strcat (buf2, "/"); + strcat (buf2, argv[0]); + if (strcmp (buf2, buf) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + else + { + strcat (buf2, argv[0] + 1); + if (strcmp (buf, buf2) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + + printf ("pass\n"); + exit (0); +} + + diff --git a/sim/testsuite/sim/cris/c/readlink3.c b/sim/testsuite/sim/cris/c/readlink3.c new file mode 100644 index 00000000000..94cff727e38 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink3.c @@ -0,0 +1,6 @@ +/* Simulator options: +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#define SYSROOTED 1 +#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink4.c b/sim/testsuite/sim/cris/c/readlink4.c new file mode 100644 index 00000000000..07a01e66453 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink4.c @@ -0,0 +1,62 @@ +/* Check for corner case: readlink of too-long name. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +void bye (const char *s, int i) +{ + fprintf (stderr, "%s: %d\n", s, i); + fflush (NULL); + abort (); +} + +int main (int argc, char *argv[]) +{ + char *buf; + char buf2[1024]; + int max, i; + + /* We assume this limit is what we see in the simulator as well. */ +#ifdef PATH_MAX + max = PATH_MAX; +#else + max = pathconf (argv[0], _PC_PATH_MAX); +#endif + + max *= 10; + + if (max <= 0) + bye ("path_max", max); + + if ((buf = malloc (max + 1)) == NULL) + bye ("malloc", 0); + + strcat (buf, argv[0]); + + if (rindex (buf, '/') == NULL) + strcat (buf, "./"); + + for (i = rindex (buf, '/') - buf + 1; i < max; i++) + buf[i] = 'a'; + + buf [i] = 0; + + i = readlink (buf, buf2, sizeof (buf2) - 1); + if (i != -1) + bye ("i", i); + + if (errno != ENAMETOOLONG) + { + perror (buf); + bye ("errno", errno); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/readlink5.c b/sim/testsuite/sim/cris/c/readlink5.c new file mode 100644 index 00000000000..11de3487111 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink5.c @@ -0,0 +1,8 @@ +/* Check that unsupported readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: ./readlink5.c.x +#xerror: +#output: Unimplemented readlink syscall (*)\n +#output: program stopped with signal 4.\n +*/ +#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink6.c b/sim/testsuite/sim/cris/c/readlink6.c new file mode 100644 index 00000000000..4bac20d8190 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink6.c @@ -0,0 +1,5 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: @exedir@/readlink6.c.x +*/ +#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink7.c b/sim/testsuite/sim/cris/c/readlink7.c new file mode 100644 index 00000000000..9c2b3b732c8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink7.c @@ -0,0 +1,6 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink8.c b/sim/testsuite/sim/cris/c/readlink8.c new file mode 100644 index 00000000000..55f6fe8541f --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink8.c @@ -0,0 +1,8 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#define SYSROOTED 1 +#include "readlink2.c" diff --git a/sim/testsuite/sim/cris/c/readlink9.c b/sim/testsuite/sim/cris/c/readlink9.c new file mode 100644 index 00000000000..27880543637 --- /dev/null +++ b/sim/testsuite/sim/cris/c/readlink9.c @@ -0,0 +1,23 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +#cc: additional_flags=-DX="@exedir@" +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + /* We assume that "sim/testsuite" isn't renamed to anything that + together with "/" is shorter than 7 characters. */ + char buf[7]; + + if (readlink("/proc/42/exe", buf, sizeof (buf)) != sizeof (buf) + || strncmp (buf, X, sizeof (buf)) != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/rename2.c b/sim/testsuite/sim/cris/c/rename2.c new file mode 100644 index 00000000000..39387d1ff31 --- /dev/null +++ b/sim/testsuite/sim/cris/c/rename2.c @@ -0,0 +1,38 @@ +/* Test some execution paths for error cases. +#cc: additional_flags=-Wl,--section-start=.startup=0x8000 + The linker option is for sake of newlib, where the default program + layout starts at address 0. We need to change the layout so + there's no memory at 0, as all sim error checking is "lazy", + depending on lack of memory mapping. */ + +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + /* Avoid getting files with random characters due to errors + elsewhere. */ + if (argc != 1 + || (argv[0][0] != '.' && argv[0][0] != '/' && argv[0][0] != 'r')) + abort (); + + if (rename (argv[0], NULL) != -1 + || errno != EFAULT) + err ("rename 1 "); + + errno = 0; + + if (rename (NULL, argv[0]) != -1 + || errno != EFAULT) + err ("rename 2"); + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/rtsigprocmask1.c b/sim/testsuite/sim/cris/c/rtsigprocmask1.c new file mode 100644 index 00000000000..0eee76845ef --- /dev/null +++ b/sim/testsuite/sim/cris/c/rtsigprocmask1.c @@ -0,0 +1,45 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented rt_sigprocmask syscall (0x3, 0x0, 0x3dff*\n +#output: program stopped with signal 4.\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + /* An invalid parameter 1 should cause this to halt the simulator. */ + pthread_sigmask (SIG_BLOCK + SIG_UNBLOCK + SIG_SETMASK, + NULL, &sigs); + printf ("xyzzy\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/rtsigsuspend1.c b/sim/testsuite/sim/cris/c/rtsigsuspend1.c new file mode 100644 index 00000000000..4a5ee3fd9c4 --- /dev/null +++ b/sim/testsuite/sim/cris/c/rtsigsuspend1.c @@ -0,0 +1,18 @@ +/* Test that TRT happens for invalid rt_sigsuspend calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigsuspend syscall arguments (0x1, 0x2)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + syscall (SYS_rt_sigsuspend, 1, 2); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched1.c b/sim/testsuite/sim/cris/c/sched1.c new file mode 100644 index 00000000000..04dae4bd5db --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched1.c @@ -0,0 +1,15 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (getpid ()) != SCHED_OTHER) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched2.c b/sim/testsuite/sim/cris/c/sched2.c new file mode 100644 index 00000000000..5371c787f77 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched2.c @@ -0,0 +1,19 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched3.c b/sim/testsuite/sim/cris/c/sched3.c new file mode 100644 index 00000000000..601e7e00eea --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched3.c @@ -0,0 +1,24 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != -1 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched4.c b/sim/testsuite/sim/cris/c/sched4.c new file mode 100644 index 00000000000..57f761fe535 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched4.c @@ -0,0 +1,24 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setparam (getpid (), &sb) == 0 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched5.c b/sim/testsuite/sim/cris/c/sched5.c new file mode 100644 index 00000000000..ddfe14d03c3 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched5.c @@ -0,0 +1,19 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +int main (void) +{ + int Min = sched_get_priority_min (SCHED_OTHER); + int Max = sched_get_priority_max (SCHED_OTHER); + if (Min != 0 || Max != 0) + { + fprintf (stderr, "min: %d, max: %d\n", Min, Max); + abort (); + } + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched6.c b/sim/testsuite/sim/cris/c/sched6.c new file mode 100644 index 00000000000..d5adedc1a35 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched6.c @@ -0,0 +1,15 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +int main (void) +{ + if (sched_yield () != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched7.c b/sim/testsuite/sim/cris/c/sched7.c new file mode 100644 index 00000000000..35d006bca6a --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched7.c @@ -0,0 +1,17 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (99) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched8.c b/sim/testsuite/sim/cris/c/sched8.c new file mode 100644 index 00000000000..cd3e06e6488 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched8.c @@ -0,0 +1,19 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (99, &sb) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sched9.c b/sim/testsuite/sim/cris/c/sched9.c new file mode 100644 index 00000000000..8499e43fb8c --- /dev/null +++ b/sim/testsuite/sim/cris/c/sched9.c @@ -0,0 +1,24 @@ +/* Check corner error case: specifying invalid scheduling policy. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_get_priority_min (-1) != -1 + || errno != EINVAL) + abort (); + + errno = 0; + + if (sched_get_priority_max (-1) != -1 + || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/seek1.c b/sim/testsuite/sim/cris/c/seek1.c new file mode 100644 index 00000000000..b22c8f9e9b1 --- /dev/null +++ b/sim/testsuite/sim/cris/c/seek1.c @@ -0,0 +1,47 @@ +/* Check that basic (ll|f)seek sim functionality works. Also uses basic + file open/write functionality. */ +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct read, write and seek.\n"; + char buf[sizeof tsttxt] = ""; + + f = fopen (fname, "w"); + if (f == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/seek2.c b/sim/testsuite/sim/cris/c/seek2.c new file mode 100644 index 00000000000..9c24dfbdb08 --- /dev/null +++ b/sim/testsuite/sim/cris/c/seek2.c @@ -0,0 +1,4 @@ +/* Simulator options: +#sim: --sysroot=@exedir@/ +*/ +#include "seek1.c" diff --git a/sim/testsuite/sim/cris/c/setrlimit1.c b/sim/testsuite/sim/cris/c/setrlimit1.c new file mode 100644 index 00000000000..747f16caa7f --- /dev/null +++ b/sim/testsuite/sim/cris/c/setrlimit1.c @@ -0,0 +1,22 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + memset (&lim, 0, sizeof lim); + + if (setrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig1.c b/sim/testsuite/sim/cris/c/sig1.c new file mode 100644 index 00000000000..55499b799eb --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig1.c @@ -0,0 +1,20 @@ +#include +#include +#include + +void +leave (int n) +{ + exit (0); +} + +int +main (void) +{ + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + signal (SIGFPE, leave); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig10.c b/sim/testsuite/sim/cris/c/sig10.c new file mode 100644 index 00000000000..d9263081c61 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig10.c @@ -0,0 +1,33 @@ +/* Check that TRT happens when trying to IGN an non-ignorable signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 9\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + signal (SIGKILL, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGKILL); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig11.c b/sim/testsuite/sim/cris/c/sig11.c new file mode 100644 index 00000000000..1661f9b409d --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig11.c @@ -0,0 +1,32 @@ +/* Check that TRT happens when getting a non-standard (realtime) signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented signal: 77\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), 77); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig12.c b/sim/testsuite/sim/cris/c/sig12.c new file mode 100644 index 00000000000..5a2e65fe9c3 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig12.c @@ -0,0 +1,38 @@ +/* Check that TRT happens for a signal sent to a non-existent process/thread, more than one thread. +#cc: additional_flags=-pthread +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + + if (pthread_create (&th_a, NULL, process, (void *) "a") != 0) + abort (); + if (kill (getpid () - 1, SIGBUS) != -1 + || errno != ESRCH + || pthread_join (th_a, &retval) != 0) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig2.c b/sim/testsuite/sim/cris/c/sig2.c new file mode 100644 index 00000000000..65596ef2eea --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig2.c @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +/* Like sig1.c, but using sigaction. */ + +void +leave (int n, siginfo_t *info, void *x) +{ + abort (); +} + +int +main (void) +{ + struct sigaction sa; + sa.sa_sigaction = leave; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + if (sigaction (SIGFPE, &sa, NULL) != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig3.c b/sim/testsuite/sim/cris/c/sig3.c new file mode 100644 index 00000000000..f6137290929 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig3.c @@ -0,0 +1,13 @@ +/* Check that TRT happens at an abort (3) call, single thread. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +int main (void) +{ + abort (); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig4.c b/sim/testsuite/sim/cris/c/sig4.c new file mode 100644 index 00000000000..6d7ec0e5cb4 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig4.c @@ -0,0 +1,30 @@ +/* Check that TRT happens at an abort (3) call, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 6\n +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + abort (); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig5.c b/sim/testsuite/sim/cris/c/sig5.c new file mode 100644 index 00000000000..674621e1722 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig5.c @@ -0,0 +1,16 @@ +/* Check that TRT happens for an uncaught non-abort signal, single thread. +#xerror: +#output: Unimplemented signal: 7\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +int main (void) +{ + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig6.c b/sim/testsuite/sim/cris/c/sig6.c new file mode 100644 index 00000000000..3862cf2ee49 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig6.c @@ -0,0 +1,32 @@ +/* Check that TRT happens at an non-abort non-caught signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 7\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig7.c b/sim/testsuite/sim/cris/c/sig7.c new file mode 100644 index 00000000000..2e70a430431 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig7.c @@ -0,0 +1,24 @@ +/* Check unsupported case of sigaction syscall. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigaction syscall (0x8, 0x3df*\n +#output: program stopped with signal 4.\n +*/ +#include +#include +#include + +int +main (void) +{ + struct sigaction sa; + sa.sa_sigaction = NULL; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + if (sigaction (SIGFPE, &sa, NULL) != 0) + abort (); + + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig8.c b/sim/testsuite/sim/cris/c/sig8.c new file mode 100644 index 00000000000..8a52b217666 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig8.c @@ -0,0 +1,19 @@ +/* Check that TRT happens for an ignored catchable signal, single thread. +#xerror: +#output: Unimplemented signal: 14\n +#output: program stopped with signal 4.\n + + Sure, it'd probably be better to support signals in single-thread too, + but that's on an as-need basis, and I don't have a need for it yet. */ + +#include +#include +#include +#include +int main (void) +{ + signal (SIGALRM, SIG_IGN); + kill (getpid (), SIGALRM); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sig9.c b/sim/testsuite/sim/cris/c/sig9.c new file mode 100644 index 00000000000..c86681b4322 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sig9.c @@ -0,0 +1,36 @@ +/* Check that TRT happens at an non-abort ignored signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + signal (SIGALRM, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGALRM); + retcode = pthread_join (th_a, &retval); + if (retcode != 0 || retval != NULL) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sigreturn1.c b/sim/testsuite/sim/cris/c/sigreturn1.c new file mode 100644 index 00000000000..ddb0d02d719 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sigreturn1.c @@ -0,0 +1,18 @@ +/* Test that TRT happens for spurious sigreturn calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sigreturn2.c b/sim/testsuite/sim/cris/c/sigreturn2.c new file mode 100644 index 00000000000..f0157f0488d --- /dev/null +++ b/sim/testsuite/sim/cris/c/sigreturn2.c @@ -0,0 +1,33 @@ +/* Check that TRT happens for spurious sigreturn calls. Multiple threads. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sjlj.c b/sim/testsuite/sim/cris/c/sjlj.c new file mode 100644 index 00000000000..141faf6e612 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sjlj.c @@ -0,0 +1,34 @@ +/* Check that setjmp and longjmp stand a chance to work; that the used machine + primitives work in the simulator. */ + +#include +#include +#include + +extern void f (void); + +int ok = 0; +jmp_buf b; + +int +main () +{ + int ret = setjmp (b); + + if (ret == 42) + ok = 100; + else if (ret == 0) + f (); + + if (ok == 100) + printf ("pass\n"); + else + printf ("fail\n"); + exit (0); +} + +void +f (void) +{ + longjmp (b, 42); +} diff --git a/sim/testsuite/sim/cris/c/sock1.c b/sim/testsuite/sim/cris/c/sock1.c new file mode 100644 index 00000000000..e59f6730523 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sock1.c @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +/* Check that socketcall is suitably stubbed. */ + +int main (void) +{ + int ret = socket (PF_INET, SOCK_STREAM, IPPROTO_TCP); + + if (ret != -1) + { + fprintf (stderr, "sock: %d\n", ret); + abort (); + } + + if (errno != ENOSYS) + { + perror ("unexpected"); + abort (); + } + + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/stat1.c b/sim/testsuite/sim/cris/c/stat1.c new file mode 100644 index 00000000000..b5d14a388e2 --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat1.c @@ -0,0 +1,16 @@ +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/stat2.c b/sim/testsuite/sim/cris/c/stat2.c new file mode 100644 index 00000000000..78c5c44f910 --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat2.c @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/stat3.c b/sim/testsuite/sim/cris/c/stat3.c new file mode 100644 index 00000000000..a248ec0864c --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat3.c @@ -0,0 +1,26 @@ +/* Simulator options: +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char path[1024] = "/"; + struct stat buf; + + strcat (path, argv[0]); + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + if (stat (path, &buf) != 0 + || !S_ISREG (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} + diff --git a/sim/testsuite/sim/cris/c/stat4.c b/sim/testsuite/sim/cris/c/stat4.c new file mode 100644 index 00000000000..62415a340e8 --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat4.c @@ -0,0 +1,28 @@ +/* Simulator options: +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ + +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char path[1024] = "/"; + struct stat buf; + + strcat (path, argv[0]); + if (lstat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + if (lstat (path, &buf) != 0 + || !S_ISREG (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} + diff --git a/sim/testsuite/sim/cris/c/stat5.c b/sim/testsuite/sim/cris/c/stat5.c new file mode 100644 index 00000000000..41ab493fd5c --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat5.c @@ -0,0 +1,20 @@ +/* Check that lstat:ing an nonexistent file works as expected. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat ("nonexistent", &buf) == 0 || errno != ENOENT) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/stat7.c b/sim/testsuite/sim/cris/c/stat7.c new file mode 100644 index 00000000000..cbd5282b70a --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat7.c @@ -0,0 +1,26 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + if (lstat (NULL, &buf) != -1 + || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat 1"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/stat8.c b/sim/testsuite/sim/cris/c/stat8.c new file mode 100644 index 00000000000..c7eb49f5403 --- /dev/null +++ b/sim/testsuite/sim/cris/c/stat8.c @@ -0,0 +1,26 @@ +/* For this test, we need to do the lstat syscall directly, or else + glibc gets a SEGV. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int ret; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + ret = syscall (SYS_lstat64, ".", NULL); + if (ret != -1 || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/syscall1.c b/sim/testsuite/sim/cris/c/syscall1.c new file mode 100644 index 00000000000..5b8cfda7b51 --- /dev/null +++ b/sim/testsuite/sim/cris/c/syscall1.c @@ -0,0 +1,19 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include + +int main (void) +{ + /* The number 166 is chosen because there's a gap for that number in + the CRIS asm/unistd.h. */ + syscall (166, 1, 2, 3, 4, 5, 6); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/syscall2.c b/sim/testsuite/sim/cris/c/syscall2.c new file mode 100644 index 00000000000..4497588dd24 --- /dev/null +++ b/sim/testsuite/sim/cris/c/syscall2.c @@ -0,0 +1,18 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include + +int main (void) +{ + /* Check special case of number 0 syscall. */ + syscall (0, 3, 2, 1, 4, 6, 5); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sysctl1.c b/sim/testsuite/sim/cris/c/sysctl1.c new file mode 100644 index 00000000000..6646faca678 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sysctl1.c @@ -0,0 +1,38 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +/* I can't seem to include the right things, so we do it brute force. */ +int main (void) +{ + static int sysctl_args[] = { 1, 4 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + if (syscall (SYS__sysctl, &scargs) != -1 + || errno != EFAULT) + abort (); + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/sysctl2.c b/sim/testsuite/sim/cris/c/sysctl2.c new file mode 100644 index 00000000000..482e5463f81 --- /dev/null +++ b/sim/testsuite/sim/cris/c/sysctl2.c @@ -0,0 +1,38 @@ +/* Check error message for invalid sysctl call. +#xerror: +#output: Unimplemented _sysctl syscall *\n +#output: program stopped with signal 4.\n +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + static int sysctl_args[] = { 99, 99 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + syscall (SYS__sysctl, &scargs); + printf ("xyzzy\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/thread2.c b/sim/testsuite/sim/cris/c/thread2.c new file mode 100644 index 00000000000..c9ad2f9214c --- /dev/null +++ b/sim/testsuite/sim/cris/c/thread2.c @@ -0,0 +1,28 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + A sanity check for syscalls resulting from + pthread_getschedparam and pthread_setschedparam. */ + +#include +#include +#include + +int main (void) +{ + struct sched_param param; + int policy; + + if (pthread_getschedparam (pthread_self (), &policy, ¶m) != 0 + || policy != SCHED_OTHER + || param.sched_priority != 0) + abort (); + + if (pthread_setschedparam (pthread_self (), SCHED_OTHER, ¶m) != 0 + || param.sched_priority != 0) + abort (); + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/thread3.c b/sim/testsuite/sim/cris/c/thread3.c new file mode 100644 index 00000000000..3b6945ad3c3 --- /dev/null +++ b/sim/testsuite/sim/cris/c/thread3.c @@ -0,0 +1,46 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + To test sched_yield in the presencs of threads. Core from ex1.c. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 10; i++) + { + if (sched_yield () != 0) + abort (); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + abort (); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + abort (); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + abort (); + printf ("pass\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/thread4.c b/sim/testsuite/sim/cris/c/thread4.c new file mode 100644 index 00000000000..cfa23279c50 --- /dev/null +++ b/sim/testsuite/sim/cris/c/thread4.c @@ -0,0 +1,50 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abb ok\n + + Testing a pthread corner case. Output will change with glibc + releases. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + + if (pthread_setcancelstate (PTHREAD_CANCEL_ENABLE, NULL) != 0) + abort (); + write (2, "a", 1); + for (i = 0; i < 10; i++) + { + sched_yield (); + pthread_testcancel (); + write (2, "b", 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, NULL); + sched_yield (); + sched_yield (); + sched_yield (); + sched_yield (); + retcode = pthread_cancel (th_a); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/thread5.c b/sim/testsuite/sim/cris/c/thread5.c new file mode 100644 index 00000000000..494251fdd39 --- /dev/null +++ b/sim/testsuite/sim/cris/c/thread5.c @@ -0,0 +1,77 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abbb ok\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + write (2, "a", 1); + write (2, "b", 1); + write (2, "b", 1); + write (2, "b", 1); + return NULL; +} + +int ok = 0; +volatile int done = 0; + +void +sigusr1 (int signum) +{ + if (signum != SIGUSR1 || !ok) + abort (); + done = 1; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + if (signal (SIGUSR1, sigusr1) != SIG_DFL) + abort (); + if (pthread_sigmask (SIG_BLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_BLOCK, &sigs, NULL) != 0) + abort (); + if (pthread_kill (pthread_self (), SIGUSR1) != 0 + || sched_yield () != 0 + || sched_yield () != 0 + || sched_yield () != 0) + abort (); + + ok = 1; + if (pthread_sigmask (SIG_UNBLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_UNBLOCK, &sigs, NULL) != 0) + abort (); + + if (!done) + abort (); + + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +} diff --git a/sim/testsuite/sim/cris/c/time1.c b/sim/testsuite/sim/cris/c/time1.c new file mode 100644 index 00000000000..3fcf0e15352 --- /dev/null +++ b/sim/testsuite/sim/cris/c/time1.c @@ -0,0 +1,46 @@ +/* Basic time functionality test: check that milliseconds are + incremented for each syscall (does not work on host). */ +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int +main (void) +{ + struct timeval t_m = {0, 0}; + struct timezone t_z = {0, 0}; + struct timeval t_m1 = {0, 0}; + int i; + + if (gettimeofday (&t_m, &t_z) != 0) + err ("gettimeofday"); + + for (i = 1; i < 10000; i++) + if (gettimeofday (&t_m1, NULL) != 0) + err ("gettimeofday 1"); + else + if (t_m1.tv_sec * 1000000 + t_m1.tv_usec + != (t_m.tv_sec * 1000000 + t_m.tv_usec + i * 1000)) + { + fprintf (stderr, "t0 (%ld, %ld), i %d, t1 (%ld, %ld)\n", + t_m.tv_sec, t_m.tv_usec, i, t_m1.tv_sec, t_m1.tv_usec); + abort (); + } + + if (time (NULL) != t_m1.tv_sec) + { + fprintf (stderr, "time != gettod\n"); + abort (); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/truncate1.c b/sim/testsuite/sim/cris/c/truncate1.c new file mode 100644 index 00000000000..477dc3d61d2 --- /dev/null +++ b/sim/testsuite/sim/cris/c/truncate1.c @@ -0,0 +1,49 @@ +/* Check that the truncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif +int +main (void) +{ + FILE *f; + const char fname[] = PREFIX "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + if (truncate (fname, strlen(tsttxt1) - 10) != 0) + { + perror ("truncate"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 10 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 10) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +} diff --git a/sim/testsuite/sim/cris/c/truncate2.c b/sim/testsuite/sim/cris/c/truncate2.c new file mode 100644 index 00000000000..a4c6470d8c7 --- /dev/null +++ b/sim/testsuite/sim/cris/c/truncate2.c @@ -0,0 +1,6 @@ +/* +#sim: --sysroot=@exedir@ +#notarget: cris*-*-elf +*/ +#define PREFIX "/" +#include "truncate1.c" diff --git a/sim/testsuite/sim/cris/c/ugetrlimit1.c b/sim/testsuite/sim/cris/c/ugetrlimit1.c new file mode 100644 index 00000000000..2a49b9589ee --- /dev/null +++ b/sim/testsuite/sim/cris/c/ugetrlimit1.c @@ -0,0 +1,21 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + + if (getrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +} -- 2.30.2