From 5e26daa4c8d0e3a31ac5edb7def49418a46c1537 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 May 2021 18:45:43 +0100 Subject: [PATCH] add in predicate mask bit detection when zeroing is enabled --- src/soc/simple/core.py | 9 +++++++-- src/soc/simple/issuer.py | 12 +++++++++--- src/soc/simple/test/test_issuer.py | 14 +++++++------- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 0db5dfa5..842b5eac 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -111,6 +111,8 @@ class NonProductionCore(Elaboratable): self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE if self.svp64_en: self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field + self.sv_pred_sm = Signal() # TODO: SIMD width + self.sv_pred_dm = Signal() # TODO: SIMD width # issue/valid/busy signalling self.ivalid_i = Signal(reset_less=True) # instruction is valid @@ -163,8 +165,11 @@ class NonProductionCore(Elaboratable): comb += v.dec.bigendian.eq(self.bigendian_i) # sigh due to SVP64 RA_OR_ZERO detection connect these too comb += v.sv_a_nz.eq(self.sv_a_nz) - if self.svp64_en and k != self.trapunit: - comb += v.sv_rm.eq(self.sv_rm) # pass through SVP64 ReMap + if self.svp64_en: + comb += v.pred_sm.eq(self.sv_pred_sm) + comb += v.pred_dm.eq(self.sv_pred_dm) + if k != self.trapunit: + comb += v.sv_rm.eq(self.sv_rm) # pass through SVP64 ReMap # ssh, cheat: trap uses the main decoder because of the rewriting self.des[self.trapunit] = self.e.do diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 21e18528..44bf3b68 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -731,9 +731,15 @@ class TestIssuerInternal(Elaboratable): sync += core.state.eq(cur_state) sync += core.raw_insn_i.eq(dec_opcode_i) sync += core.bigendian_i.eq(self.core_bigendian_i) - sync += core.sv_rm.eq(pdecode2.sv_rm) - # set RA_OR_ZERO detection in satellite decoders - sync += core.sv_a_nz.eq(pdecode2.sv_a_nz) + if self.svp64_en: + sync += core.sv_rm.eq(pdecode2.sv_rm) + # set RA_OR_ZERO detection in satellite decoders + sync += core.sv_a_nz.eq(pdecode2.sv_a_nz) + # pass predicate mask bits through to satellite decoders + # TODO: for SIMD this will be *multiple* bits + sync += core.sv_pred_sm.eq(self.srcmask[0]) + sync += core.sv_pred_dm.eq(self.dstmask[0]) + m.next = "INSN_EXECUTE" # move to "execute" # handshake with execution FSM, move to "wait" once acknowledged diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index ebc529fc..8694ba92 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -43,15 +43,15 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64)) - suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64)) + #suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64)) # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64)) suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64)) - suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64)) - suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64)) - suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64)) - suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64)) - suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64)) - suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64)) + #suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64)) # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64)) runner = unittest.TextTestRunner() -- 2.30.2