From 5e36315f3d443052c217f591c26030eb1b971109 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 20 Jun 2022 17:00:17 +0100 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index 6f7d955b9..faca26c12 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -177,7 +177,8 @@ Example The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1. -Executable demo: +Executable pseudocode demo: + ``` [[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]] ``` @@ -205,7 +206,8 @@ The vector mask set-including-first instruction is similar to set-before-first, vmsif.m v2, v3, v0.t 1 1 x x x x 1 1 v2 contents -Executable demo: +Executable pseudocode demo: + ``` [[!inline quick="yes" raw="yes" pages="openpower/sv/sif.py"]] ``` @@ -233,7 +235,8 @@ Example vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 content -Executable demo: +Executable pseudocode demo: + ``` [[!inline quick="yes" raw="yes" pages="openpower/sv/sof.py"]] ``` -- 2.30.2