From 5e56b14125292f34699b9b748d24040f6eab4fd9 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Fri, 23 Aug 2019 13:32:05 +0200
Subject: [PATCH] Add FuseSoC core description file with Nexys A7 support

---
 microwatt.core | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 microwatt.core

diff --git a/microwatt.core b/microwatt.core
new file mode 100644
index 0000000..27c7084
--- /dev/null
+++ b/microwatt.core
@@ -0,0 +1,65 @@
+CAPI=2:
+
+name : ::microwatt:0
+
+filesets:
+  core:
+    files:
+      - decode_types.vhdl
+      - wishbone_types.vhdl
+      - common.vhdl
+      - fetch1.vhdl
+      - fetch2.vhdl
+      - decode1.vhdl
+      - helpers.vhdl
+      - decode2.vhdl
+      - register_file.vhdl
+      - cr_file.vhdl
+      - crhelpers.vhdl
+      - ppc_fx_insns.vhdl
+      - sim_console.vhdl
+      - execute1.vhdl
+      - execute2.vhdl
+      - loadstore1.vhdl
+      - loadstore2.vhdl
+      - multiply.vhdl
+      - writeback.vhdl
+      - wishbone_arbiter.vhdl
+      - core.vhdl
+    file_type : vhdlSource-2008
+
+  soc:
+    files:
+      - fpga/pp_fifo.vhd
+      - fpga/pp_soc_memory.vhd
+      - fpga/pp_soc_reset.vhd
+      - fpga/pp_soc_uart.vhd
+      - fpga/pp_utilities.vhd
+      - fpga/toplevel.vhd
+      - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
+    file_type : vhdlSource-2008
+
+  nexys_a7:
+    files:
+      - fpga/nexys_a7.xdc : {file_type : xdc}
+      - fpga/clk_gen_bypass.vhd : {file_type : vhdlSource-2008}
+
+targets:
+  nexys_a7:
+    default_tool: vivado
+    filesets: [core, nexys_a7, soc]
+    parameters : [memory_size, ram_init_file]
+    tools:
+      vivado: {part : xc7a100tcsg324-1}
+    toplevel : toplevel
+
+parameters:
+  memory_size:
+    datatype    : int
+    description : On-chip memory size (bytes)
+    paramtype   : generic
+
+  ram_init_file:
+    datatype    : file
+    description : Initial on-chip RAM contents
+    paramtype   : generic
-- 
2.30.2