From 50d8d707d5b37d59183891776051394ea96b78dd Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 18:49:30 -0700 Subject: [PATCH 1/5] rewrite int/fp moves specification text to use style requested by luke https://bugs.libre-soc.org/show_bug.cgi?id=1118#c1 --- .../sv/int_fp_mv/moves_and_conversions.mdwn | 68 +++++++++++-------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 50a9d4288..9010a036d 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -33,8 +33,8 @@ Tables that are used by # Moves -These instructions perform a straight unaltered bit-level copy from one Register -File to another. +These instructions perform a copy from one register file to another, as if by +using a GPR/FPR store, followed by a FPR/GPR load. ## Move From FPR @@ -51,14 +51,7 @@ File to another. RT <- (FRB) ``` -Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754 -representation directly. This is equivalent to `stfd` followed by `ld`. -As `mffpr` is just copying bits, `FPSCR` is not affected in any way. `mffpr` is -similar to `mfvsrd`, except doesn't require VSX, which is useful for SFFS -implementations. - -Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point -operations. +The contents of `FPR[FRB]` are placed into `GPR[RT]`. Special Registers altered: @@ -66,6 +59,17 @@ Special Registers altered: CR0 (if Rc=1) ``` +Architecture Note: + +`mffpr` is equivalent to the combination of `stfd` followed by `ld`. + +Architecture Note: + +`mffpr` is a separate instruction from `mfvsrd` because `mfvsrd` requires +VSX which may not be available on simpler implementations. +Additionally, SVP64 may treat VSX instructions differently than SFFS +instructions in a future version of the architecture. + ---------- ## Move From FPR Single @@ -80,16 +84,11 @@ Special Registers altered: | PO | RT | // | FRB | XO | Rc | X-Form | ``` - RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses + RT <- [0] * 32 || SINGLE((FRB)) ``` -Move a BFP32 from a FPR to a GPR, by using `SINGLE` to extract the standard -`BFP32` form from FRB and zero-extending the result to 64-bits and storing to -RT. This is equivalent to `stfs` followed by `lwz`. -As `mffprs` is just copying the BFP32 form, `FPSCR` is not affected in any way. - -Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point -operations. +The contents of `FPR[FRB]` are converted to BFP32 by using `SINGLE`, then +zero-extended to 64-bits, and the result stored in `GPR[RT]`. Special Registers altered: @@ -97,6 +96,10 @@ Special Registers altered: CR0 (if Rc=1) ``` +Architecture Note: + +`mffprs` is equivalent to the combination of `stfs` followed by `lwz`. + ---------- \newpage{} @@ -115,11 +118,7 @@ Special Registers altered: FRT <- (RB) ``` -move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754 -representation directly. This is equivalent to `std` followed by `lfd`. -As `mtfpr` is just copying bits, `FPSCR` is not affected in any way. `mtfpr` is -similar to `mtvsrd`, except doesn't require VSX, which is useful for SFFS -implementations. +The contents of `GPR[RB]` are placed into `FPR[FRT]`. Special Registers altered: @@ -127,6 +126,17 @@ Special Registers altered: None ``` +Architecture Note: + +`mtfpr` is equivalent to the combination of `std` followed by `lfd`. + +Architecture Note: + +`mtfpr` is a separate instruction from `mtvsrd` because `mtvsrd` requires +VSX which may not be available on simpler implementations. +Additionally, SVP64 may treat VSX instructions differently than SFFS +instructions in a future version of the architecture. + ---------- ## Move To FPR Single @@ -140,13 +150,11 @@ Special Registers altered: | PO | FRT | // | RB | XO | // | X-Form | ``` - FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses + FRT <- DOUBLE((RB)[32:63]) ``` -Move a BFP32 from a GPR to a FPR, by using `DOUBLE` on the least significant -32-bits of RB to do the standard BFP32 in BFP64 trick and store the result in -FRT. This is equivalent to `stw` followed by `lfs`. -As `mtfprs` is just copying the BFP32 form, `FPSCR` is not affected in any way. +The contents of bits 32:63 of `GPR[RB]` are converted to BFP64 by using +`DOUBLE`, then the result is stored in `GPR[RT]`. Special Registers altered: @@ -154,6 +162,10 @@ Special Registers altered: None ``` +Architecture Note: + +`mtfprs` is equivalent to the combination of `stw` followed by `lfs`. + ---------- \newpage{} -- 2.30.2 From c20a7f61310a01126862f31ba1d9d364b226cf81 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 18:53:32 -0700 Subject: [PATCH 2/5] reformat markdown tables --- .../sv/int_fp_mv/moves_and_conversions.mdwn | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 9010a036d..45a2d7a2c 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -243,16 +243,16 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|----------------------|----------------------| -| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` | -| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` | -| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` | -| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` | -| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` | -| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` | -| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` | -| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` | +| Assembly Alias | Full Instruction | +|--------------------|---------------------| +| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` | +| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` | +| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` | +| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` | +| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` | +| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` | +| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` | +| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` | ---------- @@ -312,8 +312,8 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|----------------------|----------------------| +| Assembly Alias | Full Instruction | +|---------------------|---------------------| | `ctfprws FRT, RB` | `ctfpr FRT, RB, 0` | | `ctfprws. FRT, RB` | `ctfpr. FRT, RB, 0` | | `ctfpruws FRT, RB` | `ctfpr FRT, RB, 1` | @@ -403,18 +403,18 @@ are all set as normal for any GPR instructions that overflow. Key for pseudo-code: -| term | result type | definition | -|---------------------------|-------------|----------------------------------------------------------------------------------------------------| -| `fp` | -- | `f32` or `f64` (or other types from SimpleV) | -| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) | -| `uint` | -- | the unsigned integer of the same bit-width as `int` | -| `int::BITS` | `int` | the bit-width of `int` | -| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` | -| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` | -| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` | -| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` | -| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. | -| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` | +| term | result type | definition | +|---------------------------|-------------|-----------------------------------------------------------------------------------------------| +| `fp` | -- | `f32` or `f64` (or other types from SimpleV) | +| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) | +| `uint` | -- | the unsigned integer of the same bit-width as `int` | +| `int::BITS` | `int` | the bit-width of `int` | +| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` | +| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` | +| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` | +| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` | +| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. | +| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
OpenPower conversion semantics (section A.2 page 1009 (page 1035) of @@ -611,8 +611,8 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|---------------------------|----------------------------| +| Assembly Alias | Full Instruction | +|--------------------------|---------------------------| | `cffprw RT, FRB, CVM` | `cffpr RT, FRB, CVM, 0` | | `cffprw. RT, FRB, CVM` | `cffpr. RT, FRB, CVM, 0` | | `cffprwo RT, FRB, CVM` | `cffpro RT, FRB, CVM, 0` | -- 2.30.2 From 04ba9d3f0ade3be5620d0cf89dbd262668de8869 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 18:58:48 -0700 Subject: [PATCH 3/5] rename sections to match PowerISA v3.1B section 3.3.18 rename sections to match PowerISA v3.1B section 3.3.18 Move To/From Vector-Scalar Register Instructions --- openpower/sv/int_fp_mv/moves_and_conversions.mdwn | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 45a2d7a2c..2fc277943 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -31,12 +31,12 @@ Tables that are used by ---------- -# Moves +# Move To/From Floating-Point Register Instructions These instructions perform a copy from one register file to another, as if by using a GPR/FPR store, followed by a FPR/GPR load. -## Move From FPR +## Move From Floating-Point Register ``` mffpr RT, FRB @@ -72,7 +72,7 @@ instructions in a future version of the architecture. ---------- -## Move From FPR Single +## Move From Floating-Point Register Single ``` mffprs RT, FRB @@ -104,7 +104,7 @@ Architecture Note: \newpage{} -## Move To FPR +## Move To Floating-Point Register ``` mtfpr FRT, RB @@ -139,7 +139,7 @@ instructions in a future version of the architecture. ---------- -## Move To FPR Single +## Move To Floating-Point Register Single ``` mtfprs FRT, RB -- 2.30.2 From 68ba72c0faebe55080cafcc8b878b39ca81efbc3 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 19:07:36 -0700 Subject: [PATCH 4/5] change c[ft]fpr* instruction titles --- openpower/sv/int_fp_mv/moves_and_conversions.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 2fc277943..5d39da01c 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -170,14 +170,14 @@ Architecture Note: \newpage{} -# Conversions +# Conversion To/From Floating-Point Register Instructions Unlike the move instructions these instructions perform conversions between Integer and Floating Point. Truncation can therefore occur, as well as exceptions. -## Convert To FPR +## Convert To Floating-Point Register ``` ctfpr FRT, RB, IT @@ -258,7 +258,7 @@ Special Registers altered: \newpage{} -## Convert To FPR Single +## Convert To Floating-Point Register Single ``` ctfprs FRT, RB, IT @@ -466,7 +466,7 @@ Section 7.1 of the ECMAScript / JavaScript \newpage{} -## Convert From FPR +## Convert From Floating-Point Register ``` cffpr RT, FRB, CVM, IT -- 2.30.2 From 5e573680771f7a041d93d394003d6f9f08177a98 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 19:08:11 -0700 Subject: [PATCH 5/5] match v3.1B section 4.6.7.2 Floating-Point Convert To/From Integer Instructions --- openpower/sv/int_fp_mv/moves_and_conversions.mdwn | 5 ----- 1 file changed, 5 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 5d39da01c..874927446 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -172,11 +172,6 @@ Architecture Note: # Conversion To/From Floating-Point Register Instructions -Unlike the move instructions -these instructions perform conversions between Integer and -Floating Point. Truncation can therefore occur, as well -as exceptions. - ## Convert To Floating-Point Register ``` -- 2.30.2