From 5e6e553da695c0686f688125ae64a35c1bd96f47 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 14 Sep 2022 23:24:30 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 234b3f4b1..9d5b98a10 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -387,16 +387,19 @@ The biggest advantage inherent in Vertical-First is that it is very easy to introduce into compilers, because all looping, as far as programs is concerned, remains expressed as *Scalar assembler*.[^autovec] Whilst Mitch Alsup's -VVM advocates auto-vectorisation and is limited in its ability to call +VVM biggest strength is its hardware-level auto-vectorisation +but is limited in its ability to call functions, Simple-V's Vertical-First provides explicit control over the parallelism ("hphint")[^hphint] and also allows for full state to be stored/restored -(SVLR combined with LR), permitting full function calls to be made. +(SVLR combined with LR), permitting full function calls to be made +from inside Vertical-First Loops, and potentially allows arbitrarily-depth +nested VF Loops. Simple-V Vertical-First Looping requires an explicit instruction to move `SVSTATE` regfile offsets forward: `svstep`. An early version of Vectorised Branch-Conditional attempted to merge the functionality of `svstep` -into `sv.bc`: it became CISC-like and was reverted. +into `sv.bc`: it became CISC-like in its complexity and was quickly reverted. \newpage{} # Simple-V REMAP subsystem -- 2.30.2