From 5e89c7f1375221a286260d01f86d9c07796a78c7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 Jun 2020 15:26:05 +0100 Subject: [PATCH] add in TstL0CacheBuffer but disable temporarily --- src/soc/fu/compunits/compunits.py | 8 ++++---- src/soc/simple/core.py | 10 ++++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 1ffe7d8d..cfc7c80c 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -156,7 +156,7 @@ class AllFunctionUnits(Elaboratable): * type of FU required """ - def __init__(self, pi=None): + def __init__(self, pilist=None, addrwid=6): self.fus = {} for (name, qty, kls) in (('alu', 1, ALUFunctionUnit), ('cr', 1, CRFunctionUnit), @@ -166,10 +166,10 @@ class AllFunctionUnits(Elaboratable): ): for i in range(qty): self.fus["%s%d" % (name, i)] = kls() - if pi is None: + if pilist is None: return - for i in enumerate(pi): - self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi[i]) + for i, pi in enumerate(pilist): + self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid) def elaborate(self, platform): m = Module() diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 4c5f4d78..19ffc46f 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -29,6 +29,7 @@ from soc.fu.compunits.compunits import AllFunctionUnits from soc.regfile.regfiles import RegFiles from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_decoder2 import PowerDecode2 +from soc.experiment.l0_cache import TstL0CacheBuffer # test only import operator @@ -50,8 +51,12 @@ def sort_fuspecs(fuspecs): class NonProductionCore(Elaboratable): - def __init__(self): - self.fus = AllFunctionUnits() + def __init__(self, addrwid=6): + self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid) + pi = self.l0.l0.dports[0].pi + + #self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid) + self.fus = AllFunctionUnits(pilist=None, addrwid=addrwid) self.regs = RegFiles() self.pdecode = pdecode = create_pdecode() self.pdecode2 = PowerDecode2(pdecode) # instruction decoder @@ -64,6 +69,7 @@ class NonProductionCore(Elaboratable): m.submodules.pdecode2 = dec2 = self.pdecode2 m.submodules.fus = self.fus + m.submodules.l0 = l0 = self.l0 self.regs.elaborate_into(m, platform) regs = self.regs fus = self.fus.fus -- 2.30.2