From 5e8c073c0ba6921047ee762d7af14a307510bab7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 4 Sep 2022 12:05:33 +0100 Subject: [PATCH] use maxvl not vl in impicit-RS --- src/openpower/decoder/power_decoder2.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index f804438e..bd445ab0 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1272,6 +1272,7 @@ class PowerDecode2(PowerDecodeSubset): # get SVSTATE srcstep (TODO: elwidth etc.) needed below vl = Signal.like(self.state.svstate.vl) + maxvl = Signal.like(self.state.svstate.maxvl) subvl = Signal.like(self.rm_dec.rm_in.subvl) srcstep = Signal.like(self.state.svstate.srcstep) dststep = Signal.like(self.state.svstate.dststep) @@ -1318,7 +1319,7 @@ class PowerDecode2(PowerDecodeSubset): with m.If(dec_o2.reg_out.ok & dec_o2.fp_madd_en): with m.If(~self.remap_active[i]): with m.If(svdec.isvec): - comb += offs.eq(vl) # VL for Vectors + comb += offs.eq(maxvl) # MAXVL for Vectors # detect if Vectorised: add srcstep/dststep if yes. # to_reg is 7-bits, outs get dststep added, ins get srcstep with m.If(svdec.isvec): -- 2.30.2