From 5e91a9377f0c7be54ae506c1864586d680258c85 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Fri, 27 Mar 2020 12:03:26 +0200 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- 84/2d41dc696fbe5cf284303411087c1f09d2e705 | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 84/2d41dc696fbe5cf284303411087c1f09d2e705 diff --git a/84/2d41dc696fbe5cf284303411087c1f09d2e705 b/84/2d41dc696fbe5cf284303411087c1f09d2e705 new file mode 100644 index 0000000..b076d8e --- /dev/null +++ b/84/2d41dc696fbe5cf284303411087c1f09d2e705 @@ -0,0 +1,93 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 27 Mar 2020 10:02:46 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHlp7-0003QI-N4; Fri, 27 Mar 2020 10:02:45 +0000 +Received: from mout.gmx.net ([212.227.15.18]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jHlp6-0003QC-3c + for libre-riscv-dev@lists.libre-riscv.org; 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