From 5e93b52ea1b37d4c9a3dce3736f6fc4eb6fa055e Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 10:08:52 +0000
Subject: [PATCH] add explicit get of data inside sv_freg_t, float32_t etc.

---
 riscv/insns/c_fsd.h       | 2 +-
 riscv/insns/c_fsdsp.h     | 2 +-
 riscv/insns/c_fsw.h       | 2 +-
 riscv/insns/c_fswsp.h     | 2 +-
 riscv/insns/fmv_x_d.h     | 2 +-
 riscv/insns/fmv_x_w.h     | 2 +-
 riscv/insns/fnmadd_s.h    | 2 +-
 riscv/insns/fsd.h         | 2 +-
 riscv/sv_insn_redirect.cc | 5 +++++
 riscv/sv_reg.h            | 1 +
 10 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index cd8a3b0..421caa8 100644
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), ((freg_t)RVC_FRS2S).v[0]); // RVC_RS1S
+MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_FRS2S.to_uint64()); // RVC_RS1S
diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index ab3c69b..e0b523e 100644
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), ((freg_t)RVC_FRS2).v[0]);
+MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_FRS2.to_uint64());
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 988096b..6cdd419 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), ((freg_t)RVC_FRS2S).v[0]); //RVC_RS1S
+  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), RVC_FRS2S.to_uint32()); //RVC_RS1S
 } else { // c.sd
   MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_RS2S); //RVC_RS1S, 
 }
diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index fff75fc..2da9618 100644
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), ((freg_t)RVC_FRS2).v[0]);
+  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), RVC_FRS2.to_uint32());
 } else { // c.sdsp
   MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_RS2);
 }
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index e292ed0..1dd2511 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(((freg_t)FRS1).v[0]);
+WRITE_RD(FRS1.to_uint64());
diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index 987ce7b..616c7e9 100644
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(sv_reg_t(((freg_t)FRS1).v[0])));
+WRITE_RD(sext32(sv_reg_t(FRS1.to_uint32())));
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 476c9a4..c8fe05e 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(((float32_t)f32(FRS1)).v ^ F32_SIGN), f32(FRS2), f32(((float32_t)f32(FRS3)).v ^ F32_SIGN)));
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).to_uint32() ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).to_uint32() ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 16b009b..40b5b73 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
+MMU.store_uint64(insn.rs1(), insn.s_imm(), FRS2.to_uint64()); // RS1
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index a5d9942..0327fb6 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -895,3 +895,8 @@ uint32_t sv_freg_t::to_uint32() const&
     return reg.v[0];
 }
 
+uint32_t sv_float32_t::to_uint32() const&
+{
+    return reg.v;
+}
+
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 0fc1fb0..da55fea 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -108,6 +108,7 @@ public:
 public:
 
   operator float32_t() const& { return reg; }
+  uint32_t to_uint32() const&;
 };
 
 class sv_float64_t : public sv_regbase_t {
-- 
2.30.2