From 5e94f55a42807721e4dfe56e0c65d9a1583c2794 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 7 Apr 2022 15:44:17 +0100 Subject: [PATCH] remove addend1 and addend2 just add bothones and different. --- src/nmigen_gf/hdl/cldivrem.py | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py index 07e6e34..01f8c20 100644 --- a/src/nmigen_gf/hdl/cldivrem.py +++ b/src/nmigen_gf/hdl/cldivrem.py @@ -74,32 +74,30 @@ class EqualLeadingZeroCount(Elaboratable): # (unlike in the reference-code) is not necessary m = Module() - addend1 = Signal(self.width) - addend2 = Signal(self.width) + both_ones = Signal(self.width) + different = Signal(self.width) - # `both_ones` is set if both have no leading zeros so far - both_ones = self.a & self.b - # `different` is set if there are a different number of leading - # zeros so far - different = self.a ^ self.b - - # build addend1 and addend2 such that: - # * if both_ones is set, then addend1[i] and addend2[i] are both + # build both_ones and different such that: + # * if both_ones is set, then both_ones[i] and different[i] are both # ones in order to set the carry bit out. - # * if different is set, then addend1[i] and addend2[i] are both + # * if different is set, then both_ones[i] and different[i] are both # zeros in order to clear the carry bit out. - # * otherwise exactly one of addend1[i] and addend2[i] are set and + # * otherwise exactly one of both_ones[i] and different[i] are set and # the other is clear in order to propagate the carry bit from # less significant bits. - m.d.comb += addend1.eq(both_ones) - # different is zero when both_ones is set, so we don't need to - # OR-in both_ones - m.d.comb += addend2.eq(~different) + # * different is zero when both_ones is set, so we don't need to + # OR-in both_ones + + # `both_ones` is set if both have no leading zeros so far + m.d.comb += both_ones.eq(self.a & self.b) + # `different` is set if there are a different number of leading + # zeros so far + m.d.comb += different.eq(~(self.a ^ self.b)) # now [ab]use add: the last bit [carry-out] is the result csum = Signal(self.width + 1) carry_in = 1 # both have no leading zeros so far, so set carry - m.d.comb += csum.eq(addend1 + addend2 + carry_in) + m.d.comb += csum.eq(both_ones + different + carry_in) m.d.comb += self.out.eq(csum[self.width]) # out is carry-out return m -- 2.30.2