From 5e9f814d754be790aec5b69a95699a8af2654058 Mon Sep 17 00:00:00 2001 From: Xionghu Luo Date: Thu, 26 Nov 2020 23:38:33 -0600 Subject: [PATCH] rs6000: Change rs6000_expand_vector_set param rs6000_expand_vector_set could accept insert either to constant position or variable position, so change the operand to reg_or_cint_operand. gcc/ChangeLog: 2020-11-27 Xionghu Luo * config/rs6000/rs6000-call.c (altivec_expand_vec_set_builtin): Change call param 2 from type int to rtx. * config/rs6000/rs6000-protos.h (rs6000_expand_vector_set): Likewise. * config/rs6000/rs6000.c (rs6000_expand_vector_init): Change call param 2 from type int to rtx. (rs6000_expand_vector_set): Likewise. * config/rs6000/vector.md (vec_set): Support both constant and variable index vec_set. --- gcc/config/rs6000/rs6000-call.c | 2 +- gcc/config/rs6000/rs6000-protos.h | 2 +- gcc/config/rs6000/rs6000.c | 16 +++++++++------- gcc/config/rs6000/vector.md | 4 ++-- 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 1572671067a..45bc048b5c7 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -10890,7 +10890,7 @@ altivec_expand_vec_set_builtin (tree exp) op0 = force_reg (tmode, op0); op1 = force_reg (mode1, op1); - rs6000_expand_vector_set (op0, op1, elt); + rs6000_expand_vector_set (op0, op1, GEN_INT (elt)); return op0; } diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 49ab51042c5..3c4682b0e26 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -57,7 +57,7 @@ extern bool rs6000_move_128bit_ok_p (rtx []); extern bool rs6000_split_128bit_ok_p (rtx []); extern void rs6000_expand_float128_convert (rtx, rtx, bool); extern void rs6000_expand_vector_init (rtx, rtx); -extern void rs6000_expand_vector_set (rtx, rtx, int); +extern void rs6000_expand_vector_set (rtx, rtx, rtx); extern void rs6000_expand_vector_extract (rtx, rtx, rtx); extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx); extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a4979dbdd42..517467ebc63 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6788,7 +6788,8 @@ rs6000_expand_vector_init (rtx target, rtx vals) rs6000_expand_vector_init (target, copy); /* Insert variable. */ - rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var); + rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), + GEN_INT (one_var)); return; } @@ -6977,10 +6978,10 @@ rs6000_expand_vector_init (rtx target, rtx vals) emit_move_insn (target, mem); } -/* Set field ELT of TARGET to VAL. */ +/* Set field ELT_RTX of TARGET to VAL. */ void -rs6000_expand_vector_set (rtx target, rtx val, int elt) +rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx) { machine_mode mode = GET_MODE (target); machine_mode inner_mode = GET_MODE_INNER (mode); @@ -6994,7 +6995,6 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) if (VECTOR_MEM_VSX_P (mode)) { rtx insn = NULL_RTX; - rtx elt_rtx = GEN_INT (elt); if (mode == V2DFmode) insn = gen_vsx_set_v2df (target, target, val, elt_rtx); @@ -7021,8 +7021,11 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) } } + gcc_assert (CONST_INT_P (elt_rtx)); + /* Simplify setting single element vectors like V1TImode. */ - if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0) + if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) + && INTVAL (elt_rtx) == 0) { emit_move_insn (target, gen_lowpart (mode, val)); return; @@ -7045,8 +7048,7 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) /* Set permute mask to insert element into target. */ for (i = 0; i < width; ++i) - XVECEXP (mask, 0, elt*width + i) - = GEN_INT (i + 0x10); + XVECEXP (mask, 0, INTVAL (elt_rtx) * width + i) = GEN_INT (i + 0x10); x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0)); if (BYTES_BIG_ENDIAN) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 796345c80d3..7aab1887cf5 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1227,10 +1227,10 @@ (define_expand "vec_set" [(match_operand:VEC_E 0 "vlogical_operand") (match_operand: 1 "register_operand") - (match_operand 2 "const_int_operand")] + (match_operand 2 "reg_or_cint_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" { - rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); + rs6000_expand_vector_set (operands[0], operands[1], operands[2]); DONE; }) -- 2.30.2