From 5eb173304bd1cebdde0617bcc42cd4dca0b8c880 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 27 Aug 2018 16:16:58 -0700 Subject: [PATCH] anv/icl: Set Enabled Texel Offset Precision Fix bit h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/intel/genxml/gen11.xml | 5 +++++ src/intel/vulkan/genX_state.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 1b3befbbfc9..c69d7dc89c2 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3640,4 +3640,9 @@ + + + + + diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 4a175b9234d..aa5bce5a801 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device) lri.RegisterOffset = GENX(SAMPLER_MODE_num); lri.DataDWord = sampler_mode; } + + /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in + * HALF_SLICE_CHICKEN7 register. + */ + uint32_t half_slice_chicken7; + anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7), + .EnabledTexelOffsetPrecisionFix = true, + .EnabledTexelOffsetPrecisionFixMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num); + lri.DataDWord = half_slice_chicken7; + } + #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so -- 2.30.2