From 5eb5477aef6abae55dde17cc5d5f182b32bda10b Mon Sep 17 00:00:00 2001 From: klehman Date: Wed, 8 Sep 2021 09:03:13 -0400 Subject: [PATCH] initial commit of sim state class --- src/soc/simple/test/teststate.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 src/soc/simple/test/teststate.py diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py new file mode 100644 index 00000000..0520d166 --- /dev/null +++ b/src/soc/simple/test/teststate.py @@ -0,0 +1,11 @@ +class SimState: + def __init__(self, sim): + self.sim = sim + + def get_intregs(self): + self.intregs = [] + for i in range(32): + simregval = self.sim.gpr[i].asint() + self.intregs.append(simregval) + +# HDL class here with same functions -- 2.30.2