From 5ec1ae3b8a6e8ae48f51c9345e91da560694fe1e Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Thu, 3 Dec 2015 16:08:40 +0000 Subject: [PATCH] Add cost model for Exynos M1 gcc/ * config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model. * config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable. (exynosm1_regmove_cost): Likewise. (exynosm1_vector_cost): Likewise. (exynosm1_tunings): Likewise. * config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise. * config/arm/arm.c (arm_exynosm1_tune): Likewise. * config/arm/arm-cores.def: Use the Exynos M1 cost model. From-SVN: r231233 --- gcc/ChangeLog | 10 +++ gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64.c | 66 +++++++++++++++++ gcc/config/arm/aarch-cost-tables.h | 103 +++++++++++++++++++++++++++ gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm.c | 23 ++++++ 6 files changed, 204 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index de8ae8a40c9..8a7a4ec04f7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2015-12-03 Evandro Menezes + + * config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model. + * config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable. + (exynosm1_regmove_cost): Likewise. + (exynosm1_vector_cost): Likewise. + (exynosm1_tunings): Likewise. + * config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise. + * config/arm/arm.c (arm_exynos_m1_tune): Likewise. + 2015-12-03 Alan Lawrence Richard Biener diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index f8fab28d912..076574ec429 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -44,7 +44,7 @@ AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AA AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03") AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07") AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08") -AARCH64_CORE("exynos-m1", exynosm1, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa72, "0x53", "0x001") +AARCH64_CORE("exynos-m1", exynosm1, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001") AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800") AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1") AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000") diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 88f3ef8c8e8..bfbfc2a836d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -216,6 +216,22 @@ static const struct cpu_addrcost_table cortexa57_addrcost_table = 0, /* imm_offset */ }; +static const struct cpu_addrcost_table exynosm1_addrcost_table = +{ + { + 0, /* hi */ + 0, /* si */ + 0, /* di */ + 2, /* ti */ + }, + 0, /* pre_modify */ + 0, /* post_modify */ + 1, /* register_offset */ + 1, /* register_sextend */ + 2, /* register_zextend */ + 0, /* imm_offset */ +}; + static const struct cpu_addrcost_table xgene1_addrcost_table = { { @@ -262,6 +278,16 @@ static const struct cpu_regmove_cost cortexa53_regmove_cost = 2 /* FP2FP */ }; +static const struct cpu_regmove_cost exynosm1_regmove_cost = +{ + 1, /* GP2GP */ + /* Avoid the use of slow int<->fp moves for spilling by setting + their cost higher than memmov_cost (actual, 4 and 9). */ + 9, /* GP2FP */ + 9, /* FP2GP */ + 1 /* FP2FP */ +}; + static const struct cpu_regmove_cost thunderx_regmove_cost = { 2, /* GP2GP */ @@ -314,6 +340,22 @@ static const struct cpu_vector_cost cortexa57_vector_cost = 1 /* cond_not_taken_branch_cost */ }; +static const struct cpu_vector_cost exynosm1_vector_cost = +{ + 1, /* scalar_stmt_cost */ + 5, /* scalar_load_cost */ + 1, /* scalar_store_cost */ + 3, /* vec_stmt_cost */ + 3, /* vec_to_scalar_cost */ + 3, /* scalar_to_vec_cost */ + 5, /* vec_align_load_cost */ + 5, /* vec_unalign_load_cost */ + 1, /* vec_unalign_store_cost */ + 1, /* vec_store_cost */ + 1, /* cond_taken_branch_cost */ + 1 /* cond_not_taken_branch_cost */ +}; + /* Generic costs for vector insn classes. */ static const struct cpu_vector_cost xgene1_vector_cost = { @@ -470,6 +512,30 @@ static const struct tune_params cortexa72_tunings = (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; +static const struct tune_params exynosm1_tunings = +{ + &exynosm1_extra_costs, + &exynosm1_addrcost_table, + &exynosm1_regmove_cost, + &exynosm1_vector_cost, + &generic_branch_cost, + 4, /* memmov_cost */ + 3, /* issue_rate */ + (AARCH64_FUSE_NOTHING), /* fusible_ops */ + 4, /* function_align. */ + 4, /* jump_align. */ + 4, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 48, /* max_case_values. */ + 64, /* cache_line_size. */ + tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ +}; + static const struct tune_params thunderx_tunings = { &thunderx_extra_costs, diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 66e09a8b5db..850bde060b0 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -331,6 +331,109 @@ const struct cpu_cost_table cortexa57_extra_costs = } }; +const struct cpu_cost_table exynosm1_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + 0, /* shift. */ + COSTS_N_INSNS (0), /* shift_reg. */ + 0, /* arith_shift. */ + COSTS_N_INSNS (1), /* arith_shift_reg. */ + 0, /* log_shift. */ + COSTS_N_INSNS (1), /* log_shift_reg. */ + 0, /* extend. */ + COSTS_N_INSNS (1), /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* rev. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (2), /* simple. */ + COSTS_N_INSNS (3), /* flag_setting. */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (2), /* add. */ + COSTS_N_INSNS (4), /* extend_add. */ + COSTS_N_INSNS (19) /* idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (3), /* simple. */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (3), /* add. */ + COSTS_N_INSNS (4), /* extend_add. */ + COSTS_N_INSNS (35) /* idiv. */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (3), /* load. */ + COSTS_N_INSNS (4), /* load_sign_extend. */ + COSTS_N_INSNS (3), /* ldrd. */ + COSTS_N_INSNS (2), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (4), /* loadf. */ + COSTS_N_INSNS (4), /* loadd. */ + COSTS_N_INSNS (4), /* load_unaligned. */ + 0, /* store. */ + 0, /* strd. */ + 0, /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + 0, /* storef. */ + 0, /* stored. */ + 0, /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (21), /* div. */ + COSTS_N_INSNS (3), /* mult. */ + COSTS_N_INSNS (4), /* mult_addsub. */ + COSTS_N_INSNS (4), /* fma. */ + COSTS_N_INSNS (2), /* addsub. */ + COSTS_N_INSNS (0), /* fpconst. */ + COSTS_N_INSNS (0), /* neg. */ + COSTS_N_INSNS (3), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (12), /* toint. */ + COSTS_N_INSNS (7), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (34), /* div. */ + COSTS_N_INSNS (3), /* mult. */ + COSTS_N_INSNS (4), /* mult_addsub. */ + COSTS_N_INSNS (4), /* fma. */ + COSTS_N_INSNS (2), /* addsub. */ + COSTS_N_INSNS (0), /* fpconst. */ + COSTS_N_INSNS (0), /* neg. */ + COSTS_N_INSNS (3), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (12), /* toint. */ + COSTS_N_INSNS (7), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (0) /* alu. */ + } +}; + const struct cpu_cost_table xgene1_extra_costs = { /* ALU */ diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index d09707b6ed0..642c840bed7 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -169,7 +169,7 @@ ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 362329d5f37..42bf27223ef 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2006,6 +2006,29 @@ const struct tune_params arm_cortex_a57_tune = tune_params::SCHED_AUTOPREF_FULL }; +const struct tune_params arm_exynosm1_tune = +{ + arm_9e_rtx_costs, + &exynosm1_extra_costs, + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 3, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF +}; + const struct tune_params arm_xgene1_tune = { arm_9e_rtx_costs, -- 2.30.2