From 5ec4d50e64747b9c907d55cd99cb1d60a598d46b Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 4 Apr 2022 13:10:43 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 41ee321b1..d3c9d9f6a 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -172,6 +172,12 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper 3-bit Data-dependent and 3-bit Predicate-result capability (BF is 3 bits) +*Programmer's note: `mode` being XORed onto the result provides considerable +flexibility. individual bits of BFA may be copied inverted to BF by +ensuring that `mask` and `mode` have the same bit set. Also, individual +bits in BF may be set to 1 by ensuring that the required bit of `mask` +is set to zero and the same bit in `mode` is set to 1* + **crweirder** bit 19=1, bit 20=1 -- 2.30.2