From 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 19 Nov 2018 18:14:16 -0800 Subject: [PATCH] arch: cpu: Rename *FloatRegBits* to *FloatReg*. Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black --- src/arch/alpha/ev5.cc | 2 +- src/arch/alpha/registers.hh | 2 +- src/arch/alpha/remote_gdb.cc | 4 ++-- src/arch/alpha/utility.cc | 4 ++-- src/arch/arm/kvm/arm_cpu.cc | 8 ++++---- src/arch/arm/kvm/armv8_cpu.cc | 4 ++-- src/arch/arm/tracers/tarmac_parser.cc | 28 +++++++++++++-------------- src/arch/arm/tracers/tarmac_record.cc | 2 +- src/arch/arm/utility.cc | 2 +- src/arch/mips/isa/formats/fp.isa | 8 ++++---- src/arch/mips/registers.hh | 2 +- src/arch/mips/remote_gdb.cc | 12 ++++++------ src/arch/mips/utility.cc | 4 ++-- src/arch/null/registers.hh | 2 +- src/arch/power/registers.hh | 2 +- src/arch/power/remote_gdb.cc | 4 ++-- src/arch/power/utility.cc | 2 +- src/arch/riscv/registers.hh | 2 +- src/arch/riscv/remote_gdb.cc | 4 ++-- src/arch/riscv/remote_gdb.hh | 2 +- src/arch/sparc/utility.cc | 2 +- src/arch/x86/insts/micromediaop.hh | 2 +- src/arch/x86/isa/microops/mediaop.isa | 16 +++++++-------- src/arch/x86/nativetrace.cc | 4 ++-- src/arch/x86/registers.hh | 2 +- src/arch/x86/utility.cc | 2 +- src/cpu/checker/cpu.hh | 4 ++-- src/cpu/checker/cpu_impl.hh | 6 +++--- src/cpu/checker/thread_context.hh | 18 ++++++++--------- src/cpu/kvm/x86_cpu.cc | 14 ++++++-------- src/cpu/minor/exec_context.hh | 10 +++++----- src/cpu/o3/cpu.cc | 16 +++++++-------- src/cpu/o3/cpu.hh | 8 ++++---- src/cpu/o3/dyn_inst.hh | 6 +++--- src/cpu/o3/regfile.hh | 4 ++-- src/cpu/o3/thread_context.hh | 16 +++++++-------- src/cpu/o3/thread_context_impl.hh | 8 ++++---- src/cpu/simple/base.cc | 2 +- src/cpu/simple/exec_context.hh | 4 ++-- src/cpu/simple_thread.hh | 12 ++++++------ src/cpu/thread_context.cc | 8 ++++---- src/cpu/thread_context.hh | 24 +++++++++++------------ 42 files changed, 143 insertions(+), 145 deletions(-) diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 6a5d6afdc..cc0c583f0 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -88,7 +88,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatRegBits(ZeroReg, 0); + cpu->thread->setFloatReg(ZeroReg, 0); } //////////////////////////////////////////////////////////////////////// diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 218390597..07c0beeb3 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -49,7 +49,7 @@ const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; typedef RegVal IntReg; // floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; // control register file contents typedef RegVal MiscReg; diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index f3eafc0fe..9e87f1783 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -220,7 +220,7 @@ RemoteGDB::AlphaGdbRegCache::getRegs(ThreadContext *context) for (int i = 0; i < 32; ++i) #ifdef KGDB_FP_REGS - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); #else r.fpr[i] = 0; #endif @@ -243,7 +243,7 @@ RemoteGDB::AlphaGdbRegCache::setRegs(ThreadContext *context) const #ifdef KGDB_FP_REGS for (int i = 0; i < NumFloatArchRegs; ++i) { - context->setFloatRegBits(i, gdbregs.regs64[i + KGDB_REG_F0]); + context->setFloatReg(i, gdbregs.regs64[i + KGDB_REG_F0]); } #endif context->pcState(r.pc); diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc index de4b4e34d..c03e7b0da 100644 --- a/src/arch/alpha/utility.cc +++ b/src/arch/alpha/utility.cc @@ -48,7 +48,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) const int NumArgumentRegs = 6; if (number < NumArgumentRegs) { if (fp) - return tc->readFloatRegBits(16 + number); + return tc->readFloatReg(16 + number); else return tc->readIntReg(16 + number); } else { @@ -70,7 +70,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); + dest->setFloatReg(i, src->readFloatReg(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc index 69d6f8c2e..4d6b9a1b3 100644 --- a/src/arch/arm/kvm/arm_cpu.cc +++ b/src/arch/arm/kvm/arm_cpu.cc @@ -697,8 +697,8 @@ ArmKvmCPU::updateKvmStateVFP(uint64_t id, bool show_warnings) const unsigned idx_hi(idx_base + 1); const unsigned idx_lo(idx_base + 0); uint64_t value( - ((uint64_t)tc->readFloatRegBitsFlat(idx_hi) << 32) | - tc->readFloatRegBitsFlat(idx_lo)); + ((uint64_t)tc->readFloatRegFlat(idx_hi) << 32) | + tc->readFloatRegFlat(idx_lo)); setOneReg(id, value); } else if (REG_IS_VFP_CTRL(id)) { @@ -839,8 +839,8 @@ ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings) const unsigned idx_lo(idx_base + 0); uint64_t value(getOneRegU64(id)); - tc->setFloatRegBitsFlat(idx_hi, (value >> 32) & 0xFFFFFFFF); - tc->setFloatRegBitsFlat(idx_lo, value & 0xFFFFFFFF); + tc->setFloatRegFlat(idx_hi, (value >> 32) & 0xFFFFFFFF); + tc->setFloatRegFlat(idx_lo, value & 0xFFFFFFFF); } else if (REG_IS_VFP_CTRL(id)) { MiscRegIndex idx(decodeVFPCtrlReg(id)); if (idx == NUM_MISCREGS) { diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index bfd447a19..3757e2602 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -252,7 +252,7 @@ ArmV8KvmCPU::updateKvmState() const RegIndex reg_base(i * FP_REGS_PER_VFP_REG); KvmFPReg reg; for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) - reg.s[j].i = tc->readFloatRegBits(reg_base + j); + reg.s[j].i = tc->readFloatReg(reg_base + j); setOneReg(kvmFPReg(i), reg.data); DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); @@ -326,7 +326,7 @@ ArmV8KvmCPU::updateThreadContext() DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); getOneReg(kvmFPReg(i), reg.data); for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) - tc->setFloatRegBits(reg_base + j, reg.s[j].i); + tc->setFloatReg(reg_base + j, reg.s[j].i); } for (const auto &ri : getSysRegMap()) { diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 67bbb1493..860bb1b0b 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -647,35 +647,35 @@ TarmacParserRecord::TarmacParserRecordEvent::process() break; case REG_S: if (instRecord.isetstate == ISET_A64) - value_lo = thread->readFloatRegBits(it->index * 4); + value_lo = thread->readFloatReg(it->index * 4); else - value_lo = thread->readFloatRegBits(it->index); + value_lo = thread->readFloatReg(it->index); break; case REG_D: if (instRecord.isetstate == ISET_A64) - value_lo = thread->readFloatRegBits(it->index * 4) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << + value_lo = thread->readFloatReg(it->index * 4) | + (uint64_t) thread->readFloatReg(it->index * 4 + 1) << 32; else - value_lo = thread->readFloatRegBits(it->index * 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << + value_lo = thread->readFloatReg(it->index * 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 1) << 32; break; case REG_Q: check_value_hi = true; if (instRecord.isetstate == ISET_A64) { - value_lo = thread->readFloatRegBits(it->index * 4) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << + value_lo = thread->readFloatReg(it->index * 4) | + (uint64_t) thread->readFloatReg(it->index * 4 + 1) << 32; - value_hi = thread->readFloatRegBits(it->index * 4 + 2) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 3) << + value_hi = thread->readFloatReg(it->index * 4 + 2) | + (uint64_t) thread->readFloatReg(it->index * 4 + 3) << 32; } else { - value_lo = thread->readFloatRegBits(it->index * 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << + value_lo = thread->readFloatReg(it->index * 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 1) << 32; - value_hi = thread->readFloatRegBits(it->index * 2 + 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 3) << + value_hi = thread->readFloatReg(it->index * 2 + 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 3) << 32; } break; diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc index 5dbb847e5..51fbf2c0a 100644 --- a/src/arch/arm/tracers/tarmac_record.cc +++ b/src/arch/arm/tracers/tarmac_record.cc @@ -235,7 +235,7 @@ TarmacTracerRecord::TraceRegEntry::updateFloat( regValid = true; regName = "f" + std::to_string(regRelIdx); - valueLo = bitsToFloat32(thread->readFloatRegBits(regRelIdx)); + valueLo = bitsToFloat32(thread->readFloatReg(regRelIdx)); } void diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 11c3479c6..bee801358 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -170,7 +170,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) dest->setIntRegFlat(i, src->readIntRegFlat(i)); for (int i = 0; i < NumFloatRegs; i++) - dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); + dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); for (int i = 0; i < NumCCRegs; i++) dest->setCCReg(i, src->readCCReg(i)); diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index f4f05ea48..59dba6870 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -139,12 +139,12 @@ output exec {{ //Read FCSR from FloatRegFile uint32_t fcsr_bits = - cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); + cpu->tcBase()->readFloatReg(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -157,13 +157,13 @@ output exec {{ fpResetCauseBits(ExecContext *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); + cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr); } }}; diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index 633199c94..46f81d597 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -286,7 +286,7 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; typedef RegVal IntReg; // floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; // cop-0/cop-1 system control register typedef RegVal MiscReg; diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc index d490fa518..435bc0060 100644 --- a/src/arch/mips/remote_gdb.cc +++ b/src/arch/mips/remote_gdb.cc @@ -180,9 +180,9 @@ RemoteGDB::MipsGdbRegCache::getRegs(ThreadContext *context) r.badvaddr = context->readMiscRegNoEffect(MISCREG_BADVADDR); r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE); r.pc = context->pcState().pc(); - for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatRegBits(i); - r.fsr = context->readFloatRegBits(FLOATREG_FCCR); - r.fir = context->readFloatRegBits(FLOATREG_FIR); + for (int i = 0; i < 32; i++) r.fpr[i] = context->readFloatReg(i); + r.fsr = context->readFloatReg(FLOATREG_FCCR); + r.fir = context->readFloatReg(FLOATREG_FIR); } void @@ -197,9 +197,9 @@ RemoteGDB::MipsGdbRegCache::setRegs(ThreadContext *context) const context->setMiscRegNoEffect(MISCREG_BADVADDR, r.badvaddr); context->setMiscRegNoEffect(MISCREG_CAUSE, r.cause); context->pcState(r.pc); - for (int i = 0; i < 32; i++) context->setFloatRegBits(i, r.fpr[i]); - context->setFloatRegBits(FLOATREG_FCCR, r.fsr); - context->setFloatRegBits(FLOATREG_FIR, r.fir); + for (int i = 0; i < 32; i++) context->setFloatReg(i, r.fpr[i]); + context->setFloatReg(FLOATREG_FCCR, r.fsr); + context->setFloatReg(FLOATREG_FIR, r.fir); } BaseGdbRegCache* diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index c8163b752..bb20c4cc9 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -225,7 +225,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatRegBits(ZeroReg, 0); + cpu->thread->setFloatReg(ZeroReg, 0); } void @@ -247,7 +247,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; i++) - dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); + dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh index ff9e0cda6..e53cc458a 100644 --- a/src/arch/null/registers.hh +++ b/src/arch/null/registers.hh @@ -48,7 +48,7 @@ namespace NullISA { typedef RegVal IntReg; -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; typedef uint8_t CCReg; typedef RegVal MiscReg; const RegIndex ZeroReg = 0; diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index e8de218e7..909c24e96 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -49,7 +49,7 @@ const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; typedef RegVal IntReg; // Floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; typedef RegVal MiscReg; // dummy typedef since we don't have CC regs diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc index b4082e0ee..c8a71c5e7 100644 --- a/src/arch/power/remote_gdb.cc +++ b/src/arch/power/remote_gdb.cc @@ -184,7 +184,7 @@ RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context) r.gpr[i] = htobe((uint32_t)context->readIntReg(i)); for (int i = 0; i < NumFloatArchRegs; i++) - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); r.pc = htobe((uint32_t)context->pcState().pc()); r.msr = 0; // Is MSR modeled? @@ -203,7 +203,7 @@ RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const context->setIntReg(i, betoh(r.gpr[i])); for (int i = 0; i < NumFloatArchRegs; i++) - context->setFloatRegBits(i, r.fpr[i]); + context->setFloatReg(i, r.fpr[i]); context->pcState(betoh(r.pc)); // Is MSR modeled? diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc index c8ff99988..6738c1289 100644 --- a/src/arch/power/utility.cc +++ b/src/arch/power/utility.cc @@ -47,7 +47,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); + dest->setFloatReg(i, src->readFloatReg(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index a67274221..7f7cefee9 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -65,7 +65,7 @@ using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; typedef RegVal IntReg; -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; typedef uint8_t CCReg; // Not applicable to Riscv typedef RegVal MiscReg; diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 6d56a93b6..fe339ffc8 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -168,7 +168,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context) r.gpr[i] = context->readIntReg(i); r.pc = context->pcState().pc(); for (int i = 0; i < NumFloatRegs; i++) - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); r.csr_base = context->readMiscReg(0); r.fflags = context->readMiscReg(CSR_FFLAGS); @@ -186,7 +186,7 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const context->setIntReg(i, r.gpr[i]); context->pcState(r.pc); for (int i = 0; i < NumFloatRegs; i++) - context->setFloatRegBits(i, r.fpr[i]); + context->setFloatReg(i, r.fpr[i]); context->setMiscReg(0, r.csr_base); context->setMiscReg(CSR_FFLAGS, r.fflags); diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh index 739cb5a3e..adb438d24 100644 --- a/src/arch/riscv/remote_gdb.hh +++ b/src/arch/riscv/remote_gdb.hh @@ -61,7 +61,7 @@ class RemoteGDB : public BaseRemoteGDB struct { IntReg gpr[NumIntArchRegs]; IntReg pc; - FloatRegBits fpr[NumFloatRegs]; + FloatReg fpr[NumFloatRegs]; MiscReg csr_base; uint32_t fflags; diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index 8f997aabf..8b0b4ab32 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -232,7 +232,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { - dest->setFloatRegBits(i, src->readFloatRegBits(i)); + dest->setFloatReg(i, src->readFloatReg(i)); } // Would need to add condition-code regs if implemented diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh index 5cb0bdbb0..1fe871752 100644 --- a/src/arch/x86/insts/micromediaop.hh +++ b/src/arch/x86/insts/micromediaop.hh @@ -72,7 +72,7 @@ namespace X86ISA int numItems(int size) const { - return scalarOp() ? 1 : (sizeof(FloatRegBits) / size); + return scalarOp() ? 1 : (sizeof(FloatReg) / size); } bool diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index f9c6a9f9b..b8ceb02ac 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -245,7 +245,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; int offset = imm8; if (bits(src1, 0) && (ext & 0x1)) offset -= items; @@ -267,7 +267,7 @@ let {{ src2, size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / destSize; + int items = sizeof(FloatReg) / destSize; int offset = imm8; if (bits(dest, 0) && (ext & 0x1)) offset -= items; @@ -289,7 +289,7 @@ let {{ "InstRegIndex(0)", size, destSize, srcSize, ext) op_class = 'SimdMiscOp' code = ''' - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; uint64_t result = 0; int offset = (ext & 0x1) ? items : 0; for (int i = 0; i < items; i++) { @@ -325,7 +325,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = sizeof(FloatRegBits) / size; + int items = sizeof(FloatReg) / size; int options; int optionBits; if (size == 8) { @@ -342,7 +342,7 @@ let {{ for (int i = 0; i < items; i++) { uint64_t resBits; uint8_t lsel = sel & mask(optionBits); - if (lsel * size >= sizeof(FloatRegBits)) { + if (lsel * size >= sizeof(FloatReg)) { lsel -= options / 2; resBits = bits(FpSrcReg2_uqw, (lsel + 1) * sizeBits - 1, @@ -367,7 +367,7 @@ let {{ code = ''' assert(srcSize == destSize); int size = destSize; - int items = (sizeof(FloatRegBits) / size) / 2; + int items = (sizeof(FloatReg) / size) / 2; int offset = ext ? items : 0; uint64_t result = 0; for (int i = 0; i < items; i++) { @@ -393,7 +393,7 @@ let {{ op_class = 'SimdMiscOp' code = ''' assert(srcSize == destSize * 2); - int items = (sizeof(FloatRegBits) / destSize); + int items = (sizeof(FloatReg) / destSize); int destBits = destSize * 8; int srcBits = srcSize * 8; uint64_t result = 0; @@ -1091,7 +1091,7 @@ let {{ op_class = 'SimdAddOp' code = ''' int srcBits = srcSize * 8; - int items = sizeof(FloatRegBits) / srcSize; + int items = sizeof(FloatReg) / srcSize; uint64_t sum = 0; for (int i = 0; i < items; i++) { diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc index d7472ef1f..142a51cd7 100644 --- a/src/arch/x86/nativetrace.cc +++ b/src/arch/x86/nativetrace.cc @@ -90,9 +90,9 @@ X86NativeTrace::ThreadState::update(ThreadContext *tc) rip = tc->pcState().npc(); //This should be expanded if x87 registers are considered for (int i = 0; i < 8; i++) - mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i)); + mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i)); for (int i = 0; i < 32; i++) - xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i); + xmm[i] = tc->readFloatReg(X86ISA::FLOATREG_XMM_BASE + i); } diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index 893822263..8b1d59426 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -117,7 +117,7 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; //These floating point types are correct for mmx, but not //technically for x87 (80 bits) or at all for xmm (128 bits) -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; } // namespace X86ISA diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc index 33b53ca92..b430124ec 100644 --- a/src/arch/x86/utility.cc +++ b/src/arch/x86/utility.cc @@ -239,7 +239,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) dest->setIntRegFlat(i, src->readIntRegFlat(i)); //copy float regs for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); + dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); //copy condition-code regs for (int i = 0; i < NumCCRegs; ++i) dest->setCCRegFlat(i, src->readCCRegFlat(i)); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 9d6061ad8..30d17bdf6 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -199,7 +199,7 @@ class CheckerCPU : public BaseCPU, public ExecContext { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** @@ -374,7 +374,7 @@ class CheckerCPU : public BaseCPU, public ExecContext { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); setScalarResult(val); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index f6c35439b..86f022d41 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -208,7 +208,7 @@ Checker::verify(const DynInstPtr &completed_inst) // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // Check if any recent PC changes match up with anything we @@ -609,7 +609,7 @@ Checker::copyResult(const DynInstPtr &inst, break; case FloatRegClass: panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); - thread->setFloatRegBits(idx.index(), mismatch_val.asInteger()); + thread->setFloatReg(idx.index(), mismatch_val.asInteger()); break; case VecRegClass: panic_if(!mismatch_val.isVector(), "Unexpected type of result"); @@ -644,7 +644,7 @@ Checker::copyResult(const DynInstPtr &inst, break; case FloatRegClass: panic_if(!res.isScalar(), "Unexpected type of result"); - thread->setFloatRegBits(idx.index(), res.asInteger()); + thread->setFloatReg(idx.index(), res.asInteger()); break; case VecRegClass: panic_if(!res.isVector(), "Unexpected type of result"); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 8ce5a740d..99506c1c8 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -209,9 +209,9 @@ class CheckerThreadContext : public ThreadContext RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { - return actualTC->readFloatRegBits(reg_idx); + return actualTC->readFloatReg(reg_idx); } const VecRegContainer& readVecReg(const RegId& reg) const @@ -280,10 +280,10 @@ class CheckerThreadContext : public ThreadContext } void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { - actualTC->setFloatRegBits(reg_idx, val); - checkerTC->setFloatRegBits(reg_idx, val); + actualTC->setFloatReg(reg_idx, val); + checkerTC->setFloatReg(reg_idx, val); } void @@ -404,15 +404,15 @@ class CheckerThreadContext : public ThreadContext } RegVal - readFloatRegBitsFlat(int idx) + readFloatRegFlat(int idx) { - return actualTC->readFloatRegBitsFlat(idx); + return actualTC->readFloatRegFlat(idx); } void - setFloatRegBitsFlat(int idx, RegVal val) + setFloatRegFlat(int idx, RegVal val) { - actualTC->setFloatRegBitsFlat(idx, val); + actualTC->setFloatRegFlat(idx, val); } const VecRegContainer & diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index 268fb9e6d..681e14200 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -838,7 +838,7 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 8; ++i) { const unsigned reg_idx((i + top) & 0x7); const double value(bitsToFloat64( - tc->readFloatRegBits(FLOATREG_FPR(reg_idx)))); + tc->readFloatReg(FLOATREG_FPR(reg_idx)))); DPRINTF(KvmContext, "Setting KVM FP reg %i (st[%i]) := %f\n", reg_idx, i, value); X86ISA::storeFloat80(fpu.fpr[i], value); @@ -848,9 +848,9 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 16; ++i) { *(uint64_t *)&fpu.xmm[i][0] = - tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); + tc->readFloatReg(FLOATREG_XMM_LOW(i)); *(uint64_t *)&fpu.xmm[i][8] = - tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); + tc->readFloatReg(FLOATREG_XMM_HIGH(i)); } } @@ -1050,7 +1050,7 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) const double value(X86ISA::loadFloat80(fpu.fpr[i])); DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n", reg_idx, i, value); - tc->setFloatRegBits(FLOATREG_FPR(reg_idx), floatToBits64(value)); + tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value)); } // TODO: We should update the MMX state @@ -1068,10 +1068,8 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode); for (int i = 0; i < 16; ++i) { - tc->setFloatRegBits(FLOATREG_XMM_LOW(i), - *(uint64_t *)&fpu.xmm[i][0]); - tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), - *(uint64_t *)&fpu.xmm[i][8]); + tc->setFloatReg(FLOATREG_XMM_LOW(i), *(uint64_t *)&fpu.xmm[i][0]); + tc->setFloatReg(FLOATREG_XMM_HIGH(i), *(uint64_t *)&fpu.xmm[i][8]); } } diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 4cb67372e..051cf412c 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext setPredicate(true); thread.setIntReg(TheISA::ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread.setFloatRegBits(TheISA::ZeroReg, 0); + thread.setFloatReg(TheISA::ZeroReg, 0); #endif } @@ -134,7 +134,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread.readFloatRegBits(reg.index()); + return thread.readFloatReg(reg.index()); } const TheISA::VecRegContainer & @@ -190,7 +190,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread.setFloatRegBits(reg.index(), val); + thread.setFloatReg(reg.index(), val); } void @@ -443,7 +443,7 @@ class ExecContext : public ::ExecContext return other_thread->readIntReg(reg.index()); break; case FloatRegClass: - return other_thread->readFloatRegBits(reg.index()); + return other_thread->readFloatReg(reg.index()); break; case MiscRegClass: return other_thread->readMiscReg(reg.index()); @@ -466,7 +466,7 @@ class ExecContext : public ::ExecContext return other_thread->setIntReg(reg.index(), val); break; case FloatRegClass: - return other_thread->setFloatRegBits(reg.index(), val); + return other_thread->setFloatReg(reg.index(), val); break; case MiscRegClass: return other_thread->setMiscReg(reg.index(), val); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index ef3b17202..0cea74861 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1328,10 +1328,10 @@ FullO3CPU::readIntReg(PhysRegIdPtr phys_reg) template RegVal -FullO3CPU::readFloatRegBits(PhysRegIdPtr phys_reg) +FullO3CPU::readFloatReg(PhysRegIdPtr phys_reg) { fpRegfileReads++; - return regFile.readFloatRegBits(phys_reg); + return regFile.readFloatReg(phys_reg); } template @@ -1396,10 +1396,10 @@ FullO3CPU::setIntReg(PhysRegIdPtr phys_reg, RegVal val) template void -FullO3CPU::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) +FullO3CPU::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) { fpRegfileWrites++; - regFile.setFloatRegBits(phys_reg, val); + regFile.setFloatReg(phys_reg, val); } template @@ -1448,13 +1448,13 @@ FullO3CPU::readArchIntReg(int reg_idx, ThreadID tid) template RegVal -FullO3CPU::readArchFloatRegBits(int reg_idx, ThreadID tid) +FullO3CPU::readArchFloatReg(int reg_idx, ThreadID tid) { fpRegfileReads++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( RegId(FloatRegClass, reg_idx)); - return regFile.readFloatRegBits(phys_reg); + return regFile.readFloatReg(phys_reg); } template @@ -1531,13 +1531,13 @@ FullO3CPU::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) template void -FullO3CPU::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid) +FullO3CPU::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( RegId(FloatRegClass, reg_idx)); - regFile.setFloatRegBits(phys_reg, val); + regFile.setFloatReg(phys_reg, val); } template diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 30ed4ef3b..9612b3667 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -410,7 +410,7 @@ class FullO3CPU : public BaseO3CPU RegVal readIntReg(PhysRegIdPtr phys_reg); - RegVal readFloatRegBits(PhysRegIdPtr phys_reg); + RegVal readFloatReg(PhysRegIdPtr phys_reg); const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; @@ -467,7 +467,7 @@ class FullO3CPU : public BaseO3CPU void setIntReg(PhysRegIdPtr phys_reg, RegVal val); - void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); + void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); @@ -479,7 +479,7 @@ class FullO3CPU : public BaseO3CPU RegVal readArchIntReg(int reg_idx, ThreadID tid); - RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); + RegVal readArchFloatReg(int reg_idx, ThreadID tid); const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; /** Read architectural vector register for modification. */ @@ -523,7 +523,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); - void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); + void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 9793f4ead..e6dffc81d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -222,7 +222,7 @@ class BaseO3DynInst : public BaseDynInst break; case FloatRegClass: this->setFloatRegOperandBits(this->staticInst.get(), idx, - this->cpu->readFloatRegBits(prev_phys_reg)); + this->cpu->readFloatReg(prev_phys_reg)); break; case VecRegClass: this->setVecRegOperand(this->staticInst.get(), idx, @@ -280,7 +280,7 @@ class BaseO3DynInst : public BaseDynInst RegVal readFloatRegOperandBits(const StaticInst *si, int idx) { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); + return this->cpu->readFloatReg(this->_srcRegIdx[idx]); } const VecRegContainer& @@ -396,7 +396,7 @@ class BaseO3DynInst : public BaseDynInst void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); + this->cpu->setFloatReg(this->_destRegIdx[idx], val); BaseDynInst::setFloatRegOperandBits(si, idx, val); } diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 4077c99a4..163a13a25 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -194,7 +194,7 @@ class PhysRegFile } RegVal - readFloatRegBits(PhysRegIdPtr phys_reg) const + readFloatReg(PhysRegIdPtr phys_reg) const { assert(phys_reg->isFloatPhysReg()); @@ -316,7 +316,7 @@ class PhysRegFile } void - setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) + setFloatReg(PhysRegIdPtr phys_reg, RegVal val) { assert(phys_reg->isFloatPhysReg()); diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 7858f5a0a..1ab1a0876 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -189,10 +189,10 @@ class O3ThreadContext : public ThreadContext } virtual RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { - return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index()); + return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, + reg_idx)).index()); } virtual const VecRegContainer & @@ -284,10 +284,10 @@ class O3ThreadContext : public ThreadContext } virtual void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { - setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index(), val); + setFloatRegFlat(flattenRegId(RegId(FloatRegClass, + reg_idx)).index(), val); } virtual void @@ -391,8 +391,8 @@ class O3ThreadContext : public ThreadContext virtual RegVal readIntRegFlat(int idx); virtual void setIntRegFlat(int idx, RegVal val); - virtual RegVal readFloatRegBitsFlat(int idx); - virtual void setFloatRegBitsFlat(int idx, RegVal val); + virtual RegVal readFloatRegFlat(int idx); + virtual void setFloatRegFlat(int idx, RegVal val); virtual const VecRegContainer& readVecRegFlat(int idx) const; /** Read vector register operand for modification, flat indexing. */ diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 59562ba3b..2f653fa04 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -205,9 +205,9 @@ O3ThreadContext::readIntRegFlat(int reg_idx) template RegVal -O3ThreadContext::readFloatRegBitsFlat(int reg_idx) +O3ThreadContext::readFloatRegFlat(int reg_idx) { - return cpu->readArchFloatRegBits(reg_idx, thread->threadId()); + return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template @@ -264,9 +264,9 @@ O3ThreadContext::setIntRegFlat(int reg_idx, RegVal val) template void -O3ThreadContext::setFloatRegBitsFlat(int reg_idx, RegVal val) +O3ThreadContext::setFloatRegFlat(int reg_idx, RegVal val) { - cpu->setArchFloatRegBits(reg_idx, val, thread->threadId()); + cpu->setArchFloatReg(reg_idx, val, thread->threadId()); conditionalSquash(); } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c597ac904..f71277d1c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute() // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // ALPHA_ISA // check for instruction-count-based events diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index d2107b89a..3090f38a0 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -202,7 +202,7 @@ class SimpleExecContext : public ExecContext { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** Sets the bits of a floating point register of single width @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); } /** Reads a vector register. */ diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 00355c602..5c52ba28d 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -255,11 +255,11 @@ class SimpleThread : public ThreadState } RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - RegVal regVal(readFloatRegBitsFlat(flatIndex)); + RegVal regVal(readFloatRegFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -406,14 +406,14 @@ class SimpleThread : public ThreadState } void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); // XXX: Fix array out of bounds compiler error for gem5.fast // when checkercpu enabled if (flatIndex < TheISA::NumFloatRegs) - setFloatRegBitsFlat(flatIndex, val); + setFloatRegFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", reg_idx, flatIndex, val); } @@ -558,8 +558,8 @@ class SimpleThread : public ThreadState RegVal readIntRegFlat(int idx) { return intRegs[idx]; } void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } - RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } - void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } + RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } + void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } const VecRegContainer & readVecRegFlat(const RegIndex& reg) const diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 7597dbfb2..3f5781b32 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -71,8 +71,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) // Then loop through the floating point registers. for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - RegVal t1 = one->readFloatRegBits(i); - RegVal t2 = two->readFloatRegBits(i); + RegVal t1 = one->readFloatReg(i); + RegVal t2 = two->readFloatReg(i); if (t1 != t2) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -169,7 +169,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp) RegVal floatRegs[NumFloatRegs]; for (int i = 0; i < NumFloatRegs; ++i) - floatRegs[i] = tc.readFloatRegBitsFlat(i); + floatRegs[i] = tc.readFloatRegFlat(i); // This is a bit ugly, but needed to maintain backwards // compatibility. arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); @@ -213,7 +213,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) // compatibility. arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); for (int i = 0; i < NumFloatRegs; ++i) - tc.setFloatRegBitsFlat(i, floatRegs[i]); + tc.setFloatRegFlat(i, floatRegs[i]); std::vector vecRegs(NumVecRegs); UNSERIALIZE_CONTAINER(vecRegs); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 6dde68650..098fe3bb2 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -208,7 +208,7 @@ class ThreadContext // virtual RegVal readIntReg(int reg_idx) = 0; - virtual RegVal readFloatRegBits(int reg_idx) = 0; + virtual RegVal readFloatReg(int reg_idx) = 0; virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; @@ -252,7 +252,7 @@ class ThreadContext virtual void setIntReg(int reg_idx, RegVal val) = 0; - virtual void setFloatRegBits(int reg_idx, RegVal val) = 0; + virtual void setFloatReg(int reg_idx, RegVal val) = 0; virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; @@ -338,8 +338,8 @@ class ThreadContext virtual RegVal readIntRegFlat(int idx) = 0; virtual void setIntRegFlat(int idx, RegVal val) = 0; - virtual RegVal readFloatRegBitsFlat(int idx) = 0; - virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0; + virtual RegVal readFloatRegFlat(int idx) = 0; + virtual void setFloatRegFlat(int idx, RegVal val) = 0; virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; @@ -467,8 +467,8 @@ class ProxyThreadContext : public ThreadContext RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - RegVal readFloatRegBits(int reg_idx) - { return actualTC->readFloatRegBits(reg_idx); } + RegVal readFloatReg(int reg_idx) + { return actualTC->readFloatReg(reg_idx); } const VecRegContainer& readVecReg(const RegId& reg) const { return actualTC->readVecReg(reg); } @@ -528,8 +528,8 @@ class ProxyThreadContext : public ThreadContext void setIntReg(int reg_idx, RegVal val) { actualTC->setIntReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, RegVal val) - { actualTC->setFloatRegBits(reg_idx, val); } + void setFloatReg(int reg_idx, RegVal val) + { actualTC->setFloatReg(reg_idx, val); } void setVecReg(const RegId& reg, const VecRegContainer& val) { actualTC->setVecReg(reg, val); } @@ -590,11 +590,11 @@ class ProxyThreadContext : public ThreadContext void setIntRegFlat(int idx, RegVal val) { actualTC->setIntRegFlat(idx, val); } - RegVal readFloatRegBitsFlat(int idx) - { return actualTC->readFloatRegBitsFlat(idx); } + RegVal readFloatRegFlat(int idx) + { return actualTC->readFloatRegFlat(idx); } - void setFloatRegBitsFlat(int idx, RegVal val) - { actualTC->setFloatRegBitsFlat(idx, val); } + void setFloatRegFlat(int idx, RegVal val) + { actualTC->setFloatRegFlat(idx, val); } const VecRegContainer& readVecRegFlat(int id) const { return actualTC->readVecRegFlat(id); } -- 2.30.2