From 5ee0f9e26d06bd6182baa784c53a7c2b948ad482 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 24 Dec 2020 14:47:03 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index c3f9d1411..074fbdec0 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -2,8 +2,8 @@ This document provides a crash-course overview as to why SV exists, and how it works. -[SIMD is known to be harmful](https://www.sigarch.org/simd-instructions-considered-harmful/): -a seductive simplicity that is easy to implement in hardware. Even with predication added, SIMD only becomes more and more problematic with each power of two SIMD width increase introduced through an ISA revision. +SIMD, the primary method for easy parallelism of the past 30 years in Computer Architectures, is [known to be harmful](https://www.sigarch.org/simd-instructions-considered-harmful/). SIMD provides +a seductive simplicity that is easy to implement in hardware. Even with predication added, SIMD only becomes more and more problematic with each power of two SIMD width increase introduced through an ISA revision. The opcode proliferation, at O(N^6), inexorably spirals out of control in the ISA, the hardware, the software and the compilers. Cray-style variable-length Vectors on the other hand result in stunningly elegant and small loops, with no alarmingly high setup and cleanup code, where at the hardware level the microarchitecture may execute from one element right the way through to tens of thousands at a time, yet the executable remains exactly the same. Unlike in SIMD, powers of two limitations are not involved in either the hardware nor in the assembly code. -- 2.30.2