From 5ef0b7a9db3c6ec4ca191c2e9381719e1e694873 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Sun, 19 Jun 2011 21:43:41 -0400 Subject: [PATCH] inorder/dtb: make sure DTB translate correct address The DTB expects the correct PC in the ThreadContext but how if the memory accesses are speculative? Shouldn't we send along the requestor's PC to the translate functions? --- src/arch/alpha/tlb.cc | 2 +- src/cpu/inorder/resources/cache_unit.cc | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2c7e6732a..fbe188973 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -457,7 +457,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); } - if (PcPAL(tc->pcState().pc())) { + if (PcPAL(req->getPC())) { mode = (req->getFlags() & Request::ALTMODE) ? (mode_type)ALT_MODE_AM( tc->readMiscRegNoEffect(IPR_ALT_MODE)) diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 7a24348fc..39afd296e 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -426,9 +426,16 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, ThreadID tid = inst->readTid(); setupMemRequest(inst, cache_req, acc_size, flags); + + //@todo: HACK: the DTB expects the correct PC in the ThreadContext + // but how if the memory accesses are speculative? Shouldn't + // we send along the requestor's PC to the translate functions? + ThreadContext *tc = cpu->thread[tid]->getTC(); + PCState old_pc = tc->pcState(); + tc->pcState() = inst->pcState(); inst->fault = - _tlb->translateAtomic(cache_req->memReq, - cpu->thread[tid]->getTC(), tlb_mode); + _tlb->translateAtomic(cache_req->memReq, tc, tlb_mode); + tc->pcState() = old_pc; if (inst->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " -- 2.30.2