From 5ef408dfe10f2a4e6253b67f8eeded5ba07319dd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 Apr 2022 14:05:55 +0100 Subject: [PATCH] doh --- src/ls2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index 993186f..89d6c06 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -795,7 +795,7 @@ class DDR3SoC(SoC, Elaboratable): # and at the moment that's just UART tx/rx. ports = [] ports += [self.uart.tx_o, self.uart.rx_i] - for hr in self.hyperramL + for hr in self.hyperram: ports += list(hr.ports()) if hasattr(self, "ddrphy"): if hasattr(self.ddrphy, "pads"): # real PHY -- 2.30.2