From 5f045278ba39586a0ef5cb3a6f45053eafac4f9c Mon Sep 17 00:00:00 2001 From: "mtnolan2640@5b3e5887a309d4a2372aaf5e76b851870f15ca92" Date: Mon, 24 Feb 2020 16:37:29 +0000 Subject: [PATCH] --- 3d_gpu/architecture.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn index a201b8677..308725846 100644 --- a/3d_gpu/architecture.mdwn +++ b/3d_gpu/architecture.mdwn @@ -32,6 +32,10 @@ This means that in low clock rate modes the length of the whole pipeline may be The only reason why this ingenious and elegant trick (deployed first by IBM in the 1990s) can be considered is down to the fact that the 6600 Style Dependency Matrices do not care about actual completion time, they only care about availability of the result. +# Decoder + +TODO, see [[architecture/decoder]] + # Memory and Cache arrangement Section TODO, with own page [[architecture/memory_and_cache]] LD/ST accesses are controlled by the 6600-style Dependency Matrices -- 2.30.2