From 5f26b515c429bc536189c1f03ab48f38ef11d3ff Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 5 Jul 2022 17:31:35 +0100
Subject: [PATCH]

---
 openpower/sv/cr_int_predication.mdwn | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 5e34b681f..0a46d8389 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -105,7 +105,8 @@ mode is encoded in XO and is 4 bits
     n1 = mask[1] & (mode[1] == creg[1])
     n2 = mask[2] & (mode[2] == creg[2])
     n3 = mask[3] & (mode[3] == creg[3])
-    result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+    n = (n0||n1||n2||n3) & mask
+    result = (n != 0) if M else (n == mask)
     RT[63] = result # MSB0 numbering, 63 is LSB
     If Rc:
         CR0 = analyse(RT)
@@ -232,7 +233,8 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
     n3 = mask[3] & (mode[3] == creg[3])
     BF = BT[2:4] # select CR
     bit = BT[0:1] # select bit of CR
-    result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+    n = (n0||n1||n2||n3) & mask
+    result = (n != 0) if M else (n == mask)
     CR{BF}[bit] = result
 
 When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
@@ -278,7 +280,8 @@ operand) elwidth field still sets the Integer element size as usual
         n2 = mask[2] & (mode[2] == creg[2])
         n3 = mask[3] & (mode[3] == creg[3])
         # OR or AND to a single bit
-        result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+        n = (n0||n1||n2||n3) & mask
+        result = (n != 0) if M else (n == mask)
         if RT.isvec:
             # TODO: RT.elwidth override to be also added here
             # note, yes, really, the CR's elwidth field determines
@@ -371,8 +374,6 @@ results are set to zero.
             idx, boff = 0, i
         iregs[RT+idx][60-boff*4:63-boff*4] = result
 
-
-
 # v3.1 setbc instructions
 
 There are additional setb conditional instructions in v3.1 (p129)
-- 
2.30.2