From 5f30a8795d9a3b2c4ebaaa16ecf186e35e82a04b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 17:47:05 -0700 Subject: [PATCH] Tidy up --- frontends/aiger/aigerparse.cc | 2 +- passes/techmap/abc9.cc | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4e3f5e7c9..b9ab6fc09 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -361,7 +361,7 @@ void AigerReader::parse_xaiger() } } else if (c == 'r') { - uint32_t dataSize = parse_xaiger_literal(f); + /*uint32_t dataSize =*/ parse_xaiger_literal(f); uint32_t flopNum = parse_xaiger_literal(f); f.ignore(flopNum * sizeof(uint32_t)); log_assert(inputs.size() >= flopNum); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 18f860e36..67d0981f4 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -561,11 +561,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { - //if (w->name == "\\__dummy_o__") { - // log("Don't call ABC as there is nothing to map.\n"); - // goto cleanup; - //} - // Attempt another wideports_split here because there // exists the possibility that different bits of a port // could be an input and output, therefore parse_xiager() @@ -935,7 +930,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // log("Don't call ABC as there is nothing to map.\n"); //} -cleanup: if (cleanup) { log("Removing temp directory.\n"); -- 2.30.2