From 5f71414fc941f0d390c03633f1a53534807cfca6 Mon Sep 17 00:00:00 2001 From: Luca Barbieri Date: Sat, 20 Feb 2010 17:43:31 +0100 Subject: [PATCH] nv40: use NV34TCL_ constants where available It was decided to just use the NV34TCL_ constants for constants common between nv30 and nv40, and deprecate the NV40TCL_ versions. This patch changes the nv40 driver to use NV34TCL_ constants for common functionality. This reduces differences between nv30 and nv40 to ease further unification. --- src/gallium/drivers/nv40/nv40_draw.c | 40 +++--- src/gallium/drivers/nv40/nv40_fragprog.c | 8 +- src/gallium/drivers/nv40/nv40_fragtex.c | 30 ++--- src/gallium/drivers/nv40/nv40_query.c | 10 +- src/gallium/drivers/nv40/nv40_screen.c | 14 +- src/gallium/drivers/nv40/nv40_state.c | 122 +++++++++--------- src/gallium/drivers/nv40/nv40_state_blend.c | 2 +- src/gallium/drivers/nv40/nv40_state_fb.c | 36 +++--- src/gallium/drivers/nv40/nv40_state_scissor.c | 2 +- src/gallium/drivers/nv40/nv40_state_stipple.c | 6 +- .../drivers/nv40/nv40_state_viewport.c | 2 +- src/gallium/drivers/nv40/nv40_state_zsa.c | 4 +- src/gallium/drivers/nv40/nv40_vbo.c | 74 +++++------ src/gallium/drivers/nv40/nv40_vertprog.c | 22 ++-- 14 files changed, 186 insertions(+), 186 deletions(-) diff --git a/src/gallium/drivers/nv40/nv40_draw.c b/src/gallium/drivers/nv40/nv40_draw.c index 48bd84d16c5..849f24fe402 100644 --- a/src/gallium/drivers/nv40/nv40_draw.c +++ b/src/gallium/drivers/nv40/nv40_draw.c @@ -44,29 +44,29 @@ nv40_render_vertex(struct nv40_context *nv40, const struct vertex_header *v) case EMIT_OMIT: break; case EMIT_1F: - BEGIN_RING(chan, curie, NV40TCL_VTX_ATTR_1F(hw), 1); + BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_1F(hw), 1); OUT_RING (chan, fui(v->data[idx][0])); break; case EMIT_2F: - BEGIN_RING(chan, curie, NV40TCL_VTX_ATTR_2F_X(hw), 2); + BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_2F_X(hw), 2); OUT_RING (chan, fui(v->data[idx][0])); OUT_RING (chan, fui(v->data[idx][1])); break; case EMIT_3F: - BEGIN_RING(chan, curie, NV40TCL_VTX_ATTR_3F_X(hw), 3); + BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_3F_X(hw), 3); OUT_RING (chan, fui(v->data[idx][0])); OUT_RING (chan, fui(v->data[idx][1])); OUT_RING (chan, fui(v->data[idx][2])); break; case EMIT_4F: - BEGIN_RING(chan, curie, NV40TCL_VTX_ATTR_4F_X(hw), 4); + BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_4F_X(hw), 4); OUT_RING (chan, fui(v->data[idx][0])); OUT_RING (chan, fui(v->data[idx][1])); OUT_RING (chan, fui(v->data[idx][2])); OUT_RING (chan, fui(v->data[idx][3])); break; case EMIT_4UB: - BEGIN_RING(chan, curie, NV40TCL_VTX_ATTR_4UB(hw), 1); + BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_4UB(hw), 1); OUT_RING (chan, pack_ub4(float_to_ubyte(v->data[idx][0]), float_to_ubyte(v->data[idx][1]), float_to_ubyte(v->data[idx][2]), @@ -93,7 +93,7 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim, /* Ensure there's room for 4xfloat32 + potentially 3 begin/end */ if (AVAIL_RING(chan) < ((count * 20) + 6)) { - if (rs->prim != NV40TCL_BEGIN_END_STOP) { + if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { NOUVEAU_ERR("AIII, missed flush\n"); assert(0); } @@ -103,12 +103,12 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim, /* Switch primitive modes if necessary */ if (rs->prim != mode) { - if (rs->prim != NV40TCL_BEGIN_END_STOP) { - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); - OUT_RING (chan, NV40TCL_BEGIN_END_STOP); + if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); + OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, mode); rs->prim = mode; } @@ -121,28 +121,28 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim, * off the primitive now. */ if (AVAIL_RING(chan) < ((count * 20) + 6)) { - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); - OUT_RING (chan, NV40TCL_BEGIN_END_STOP); - rs->prim = NV40TCL_BEGIN_END_STOP; + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); + OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); + rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; } } static void nv40_render_point(struct draw_stage *draw, struct prim_header *prim) { - nv40_render_prim(draw, prim, NV40TCL_BEGIN_END_POINTS, 1); + nv40_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_POINTS, 1); } static void nv40_render_line(struct draw_stage *draw, struct prim_header *prim) { - nv40_render_prim(draw, prim, NV40TCL_BEGIN_END_LINES, 2); + nv40_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_LINES, 2); } static void nv40_render_tri(struct draw_stage *draw, struct prim_header *prim) { - nv40_render_prim(draw, prim, NV40TCL_BEGIN_END_TRIANGLES, 3); + nv40_render_prim(draw, prim, NV34TCL_VERTEX_BEGIN_END_TRIANGLES, 3); } static void @@ -154,10 +154,10 @@ nv40_render_flush(struct draw_stage *draw, unsigned flags) struct nouveau_channel *chan = screen->base.channel; struct nouveau_grobj *curie = screen->curie; - if (rs->prim != NV40TCL_BEGIN_END_STOP) { - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); - OUT_RING (chan, NV40TCL_BEGIN_END_STOP); - rs->prim = NV40TCL_BEGIN_END_STOP; + if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) { + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); + OUT_RING (chan, NV34TCL_VERTEX_BEGIN_END_STOP); + rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP; } } diff --git a/src/gallium/drivers/nv40/nv40_fragprog.c b/src/gallium/drivers/nv40/nv40_fragprog.c index dc24f9b08a5..d881fea6f5f 100644 --- a/src/gallium/drivers/nv40/nv40_fragprog.c +++ b/src/gallium/drivers/nv40/nv40_fragprog.c @@ -920,12 +920,12 @@ nv40_fragprog_validate(struct nv40_context *nv40) nv40_fragprog_upload(nv40, fp); so = so_new(2, 2, 1); - so_method(so, nv40->screen->curie, NV40TCL_FP_ADDRESS, 1); + so_method(so, nv40->screen->curie, NV34TCL_FP_ACTIVE_PROGRAM, 1); so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0, - NV40TCL_FP_ADDRESS_DMA1); - so_method(so, nv40->screen->curie, NV40TCL_FP_CONTROL, 1); + NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, + NV34TCL_FP_ACTIVE_PROGRAM_DMA1); + so_method(so, nv40->screen->curie, NV34TCL_FP_CONTROL, 1); so_data (so, fp->fp_control); so_ref(so, &fp->so); so_ref(NULL, &so); diff --git a/src/gallium/drivers/nv40/nv40_fragtex.c b/src/gallium/drivers/nv40/nv40_fragtex.c index b60118922a2..44bf4333bd6 100644 --- a/src/gallium/drivers/nv40/nv40_fragtex.c +++ b/src/gallium/drivers/nv40/nv40_fragtex.c @@ -7,12 +7,12 @@ TRUE, \ PIPE_FORMAT_##m, \ NV40TCL_TEX_FORMAT_FORMAT_##tf, \ - (NV40TCL_TEX_SWIZZLE_S0_X_##ts0x | NV40TCL_TEX_SWIZZLE_S0_Y_##ts0y | \ - NV40TCL_TEX_SWIZZLE_S0_Z_##ts0z | NV40TCL_TEX_SWIZZLE_S0_W_##ts0w | \ - NV40TCL_TEX_SWIZZLE_S1_X_##ts1x | NV40TCL_TEX_SWIZZLE_S1_Y_##ts1y | \ - NV40TCL_TEX_SWIZZLE_S1_Z_##ts1z | NV40TCL_TEX_SWIZZLE_S1_W_##ts1w), \ - ((NV40TCL_TEX_FILTER_SIGNED_RED*sx) | (NV40TCL_TEX_FILTER_SIGNED_GREEN*sy) | \ - (NV40TCL_TEX_FILTER_SIGNED_BLUE*sz) | (NV40TCL_TEX_FILTER_SIGNED_ALPHA*sw)) \ + (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y | \ + NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w | \ + NV34TCL_TX_SWIZZLE_S1_X_##ts1x | NV34TCL_TX_SWIZZLE_S1_Y_##ts1y | \ + NV34TCL_TX_SWIZZLE_S1_Z_##ts1z | NV34TCL_TX_SWIZZLE_S1_W_##ts1w), \ + ((NV34TCL_TX_FILTER_SIGNED_RED*sx) | (NV34TCL_TX_FILTER_SIGNED_GREEN*sy) | \ + (NV34TCL_TX_FILTER_SIGNED_BLUE*sz) | (NV34TCL_TX_FILTER_SIGNED_ALPHA*sw)) \ } struct nv40_texture_format { @@ -81,20 +81,20 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit) txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT); if (1) /* XXX */ - txf |= NV40TCL_TEX_FORMAT_NO_BORDER; + txf |= NV34TCL_TX_FORMAT_NO_BORDER; switch (pt->target) { case PIPE_TEXTURE_CUBE: - txf |= NV40TCL_TEX_FORMAT_CUBIC; + txf |= NV34TCL_TX_FORMAT_CUBIC; /* fall-through */ case PIPE_TEXTURE_2D: - txf |= NV40TCL_TEX_FORMAT_DIMS_2D; + txf |= NV34TCL_TX_FORMAT_DIMS_2D; break; case PIPE_TEXTURE_3D: - txf |= NV40TCL_TEX_FORMAT_DIMS_3D; + txf |= NV34TCL_TX_FORMAT_DIMS_3D; break; case PIPE_TEXTURE_1D: - txf |= NV40TCL_TEX_FORMAT_DIMS_1D; + txf |= NV34TCL_TX_FORMAT_DIMS_1D; break; default: NOUVEAU_ERR("Unknown target %d\n", pt->target); @@ -111,15 +111,15 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit) txs = tf->swizzle; so = so_new(2, 9, 2); - so_method(so, nv40->screen->curie, NV40TCL_TEX_OFFSET(unit), 8); + so_method(so, nv40->screen->curie, NV34TCL_TX_OFFSET(unit), 8); so_reloc (so, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0); so_reloc (so, bo, txf, tex_flags | NOUVEAU_BO_OR, - NV40TCL_TEX_FORMAT_DMA0, NV40TCL_TEX_FORMAT_DMA1); + NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1); so_data (so, ps->wrap); so_data (so, NV40TCL_TEX_ENABLE_ENABLE | ps->en); so_data (so, txs); so_data (so, ps->filt | tf->sign | 0x2000 /*voodoo*/); - so_data (so, (pt->width0 << NV40TCL_TEX_SIZE0_W_SHIFT) | + so_data (so, (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0); so_data (so, ps->bcol); so_method(so, nv40->screen->curie, NV40TCL_TEX_SIZE1(unit), 1); @@ -142,7 +142,7 @@ nv40_fragtex_validate(struct nv40_context *nv40) samplers &= ~(1 << unit); so = so_new(1, 1, 0); - so_method(so, nv40->screen->curie, NV40TCL_TEX_ENABLE(unit), 1); + so_method(so, nv40->screen->curie, NV34TCL_TX_ENABLE(unit), 1); so_data (so, 0); so_ref(so, &nv40->state.hw[NV40_STATE_FRAGTEX0 + unit]); state->dirty |= (1ULL << (NV40_STATE_FRAGTEX0 + unit)); diff --git a/src/gallium/drivers/nv40/nv40_query.c b/src/gallium/drivers/nv40/nv40_query.c index 8ed4a67dd03..45c5468537b 100644 --- a/src/gallium/drivers/nv40/nv40_query.c +++ b/src/gallium/drivers/nv40/nv40_query.c @@ -60,9 +60,9 @@ nv40_query_begin(struct pipe_context *pipe, struct pipe_query *pq) assert(0); nouveau_notifier_reset(nv40->screen->query, q->object->start); - BEGIN_RING(chan, curie, NV40TCL_QUERY_RESET, 1); + BEGIN_RING(chan, curie, NV34TCL_QUERY_RESET, 1); OUT_RING (chan, 1); - BEGIN_RING(chan, curie, NV40TCL_QUERY_UNK17CC, 1); + BEGIN_RING(chan, curie, NV34TCL_QUERY_UNK17CC, 1); OUT_RING (chan, 1); q->ready = FALSE; @@ -77,9 +77,9 @@ nv40_query_end(struct pipe_context *pipe, struct pipe_query *pq) struct nouveau_channel *chan = screen->base.channel; struct nouveau_grobj *curie = screen->curie; - BEGIN_RING(chan, curie, NV40TCL_QUERY_GET, 1); - OUT_RING (chan, (0x01 << NV40TCL_QUERY_GET_UNK24_SHIFT) | - ((q->object->start * 32) << NV40TCL_QUERY_GET_OFFSET_SHIFT)); + BEGIN_RING(chan, curie, NV34TCL_QUERY_GET, 1); + OUT_RING (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) | + ((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT)); FIRE_RING(chan); } diff --git a/src/gallium/drivers/nv40/nv40_screen.c b/src/gallium/drivers/nv40/nv40_screen.c index dbcc33d8d9e..9c49e2b6ec0 100644 --- a/src/gallium/drivers/nv40/nv40_screen.c +++ b/src/gallium/drivers/nv40/nv40_screen.c @@ -264,23 +264,23 @@ nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) /* Static curie initialisation */ so = so_new(16, 25, 0); - so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1); + so_method(so, screen->curie, NV34TCL_DMA_NOTIFY, 1); so_data (so, screen->sync->handle); - so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2); + so_method(so, screen->curie, NV34TCL_DMA_TEXTURE0, 2); so_data (so, chan->vram->handle); so_data (so, chan->gart->handle); - so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1); + so_method(so, screen->curie, NV34TCL_DMA_COLOR1, 1); so_data (so, chan->vram->handle); - so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2); + so_method(so, screen->curie, NV34TCL_DMA_COLOR0, 2); so_data (so, chan->vram->handle); so_data (so, chan->vram->handle); - so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2); + so_method(so, screen->curie, NV34TCL_DMA_VTXBUF0, 2); so_data (so, chan->vram->handle); so_data (so, chan->gart->handle); - so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2); + so_method(so, screen->curie, NV34TCL_DMA_FENCE, 2); so_data (so, 0); so_data (so, screen->query->handle); - so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2); + so_method(so, screen->curie, NV34TCL_DMA_IN_MEMORY7, 2); so_data (so, chan->vram->handle); so_data (so, chan->vram->handle); so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2); diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c index ee471e6ce4c..3db000a219d 100644 --- a/src/gallium/drivers/nv40/nv40_state.c +++ b/src/gallium/drivers/nv40/nv40_state.c @@ -19,7 +19,7 @@ nv40_blend_state_create(struct pipe_context *pipe, struct nouveau_stateobj *so = so_new(5, 8, 0); if (cso->rt[0].blend_enable) { - so_method(so, curie, NV40TCL_BLEND_ENABLE, 3); + so_method(so, curie, NV34TCL_BLEND_FUNC_ENABLE, 3); so_data (so, 1); so_data (so, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) | nvgl_blend_func(cso->rt[0].rgb_src_factor)); @@ -29,26 +29,26 @@ nv40_blend_state_create(struct pipe_context *pipe, so_data (so, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 | nvgl_blend_eqn(cso->rt[0].rgb_func)); } else { - so_method(so, curie, NV40TCL_BLEND_ENABLE, 1); + so_method(so, curie, NV34TCL_BLEND_FUNC_ENABLE, 1); so_data (so, 0); } - so_method(so, curie, NV40TCL_COLOR_MASK, 1); + so_method(so, curie, NV34TCL_COLOR_MASK, 1); so_data (so, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) | ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) | ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) | ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 << 0) : 0))); if (cso->logicop_enable) { - so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2); + so_method(so, curie, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2); so_data (so, 1); so_data (so, nvgl_logicop_func(cso->logicop_func)); } else { - so_method(so, curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1); + so_method(so, curie, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1); so_data (so, 0); } - so_method(so, curie, NV40TCL_DITHER_ENABLE, 1); + so_method(so, curie, NV34TCL_DITHER_ENABLE, 1); so_data (so, cso->dither ? 1 : 0); so_ref(so, &bso->so); @@ -82,19 +82,19 @@ wrap_mode(unsigned wrap) { switch (wrap) { case PIPE_TEX_WRAP_REPEAT: - ret = NV40TCL_TEX_WRAP_S_REPEAT; + ret = NV34TCL_TX_WRAP_S_REPEAT; break; case PIPE_TEX_WRAP_MIRROR_REPEAT: - ret = NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT; + ret = NV34TCL_TX_WRAP_S_MIRRORED_REPEAT; break; case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE; + ret = NV34TCL_TX_WRAP_S_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - ret = NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER; + ret = NV34TCL_TX_WRAP_S_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_CLAMP: - ret = NV40TCL_TEX_WRAP_S_CLAMP; + ret = NV34TCL_TX_WRAP_S_CLAMP; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE; @@ -107,11 +107,11 @@ wrap_mode(unsigned wrap) { break; default: NOUVEAU_ERR("unknown wrap mode: %d\n", wrap); - ret = NV40TCL_TEX_WRAP_S_REPEAT; + ret = NV34TCL_TX_WRAP_S_REPEAT; break; } - return ret >> NV40TCL_TEX_WRAP_S_SHIFT; + return ret >> NV34TCL_TX_WRAP_S_SHIFT; } static void * @@ -127,9 +127,9 @@ nv40_sampler_state_create(struct pipe_context *pipe, if (!cso->normalized_coords) ps->fmt |= NV40TCL_TEX_FORMAT_RECT; - ps->wrap = ((wrap_mode(cso->wrap_s) << NV40TCL_TEX_WRAP_S_SHIFT) | - (wrap_mode(cso->wrap_t) << NV40TCL_TEX_WRAP_T_SHIFT) | - (wrap_mode(cso->wrap_r) << NV40TCL_TEX_WRAP_R_SHIFT)); + ps->wrap = ((wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) | + (wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) | + (wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT)); ps->en = 0; if (cso->max_anisotropy >= 2) { @@ -160,11 +160,11 @@ nv40_sampler_state_create(struct pipe_context *pipe, switch (cso->mag_img_filter) { case PIPE_TEX_FILTER_LINEAR: - filter |= NV40TCL_TEX_FILTER_MAG_LINEAR; + filter |= NV34TCL_TX_FILTER_MAGNIFY_LINEAR; break; case PIPE_TEX_FILTER_NEAREST: default: - filter |= NV40TCL_TEX_FILTER_MAG_NEAREST; + filter |= NV34TCL_TX_FILTER_MAGNIFY_NEAREST; break; } @@ -172,14 +172,14 @@ nv40_sampler_state_create(struct pipe_context *pipe, case PIPE_TEX_FILTER_LINEAR: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST; + filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR; + filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV40TCL_TEX_FILTER_MIN_LINEAR; + filter |= NV34TCL_TX_FILTER_MINIFY_LINEAR; break; } break; @@ -187,14 +187,14 @@ nv40_sampler_state_create(struct pipe_context *pipe, default: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST; + filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR; + filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV40TCL_TEX_FILTER_MIN_NEAREST; + filter |= NV34TCL_TX_FILTER_MINIFY_NEAREST; break; } break; @@ -219,28 +219,28 @@ nv40_sampler_state_create(struct pipe_context *pipe, if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) { switch (cso->compare_func) { case PIPE_FUNC_NEVER: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NEVER; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NEVER; break; case PIPE_FUNC_GREATER: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GREATER; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GREATER; break; case PIPE_FUNC_EQUAL: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_EQUAL; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_EQUAL; break; case PIPE_FUNC_GEQUAL: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_GEQUAL; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_GEQUAL; break; case PIPE_FUNC_LESS: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LESS; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LESS; break; case PIPE_FUNC_NOTEQUAL: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_NOTEQUAL; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_NOTEQUAL; break; case PIPE_FUNC_LEQUAL: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_LEQUAL; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_LEQUAL; break; case PIPE_FUNC_ALWAYS: - ps->wrap |= NV40TCL_TEX_WRAP_RCOMP_ALWAYS; + ps->wrap |= NV34TCL_TX_WRAP_RCOMP_ALWAYS; break; default: break; @@ -319,66 +319,66 @@ nv40_rasterizer_state_create(struct pipe_context *pipe, * multisample */ - so_method(so, curie, NV40TCL_SHADE_MODEL, 1); - so_data (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT : - NV40TCL_SHADE_MODEL_SMOOTH); + so_method(so, curie, NV34TCL_SHADE_MODEL, 1); + so_data (so, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT : + NV34TCL_SHADE_MODEL_SMOOTH); - so_method(so, curie, NV40TCL_LINE_WIDTH, 2); + so_method(so, curie, NV34TCL_LINE_WIDTH, 2); so_data (so, (unsigned char)(cso->line_width * 8.0) & 0xff); so_data (so, cso->line_smooth ? 1 : 0); - so_method(so, curie, NV40TCL_LINE_STIPPLE_ENABLE, 2); + so_method(so, curie, NV34TCL_LINE_STIPPLE_ENABLE, 2); so_data (so, cso->line_stipple_enable ? 1 : 0); so_data (so, (cso->line_stipple_pattern << 16) | cso->line_stipple_factor); - so_method(so, curie, NV40TCL_POINT_SIZE, 1); + so_method(so, curie, NV34TCL_POINT_SIZE, 1); so_data (so, fui(cso->point_size)); - so_method(so, curie, NV40TCL_POLYGON_MODE_FRONT, 6); + so_method(so, curie, NV34TCL_POLYGON_MODE_FRONT, 6); if (cso->front_winding == PIPE_WINDING_CCW) { so_data(so, nvgl_polygon_mode(cso->fill_ccw)); so_data(so, nvgl_polygon_mode(cso->fill_cw)); switch (cso->cull_mode) { case PIPE_WINDING_CCW: - so_data(so, NV40TCL_CULL_FACE_FRONT); + so_data(so, NV34TCL_CULL_FACE_FRONT); break; case PIPE_WINDING_CW: - so_data(so, NV40TCL_CULL_FACE_BACK); + so_data(so, NV34TCL_CULL_FACE_BACK); break; case PIPE_WINDING_BOTH: - so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK); + so_data(so, NV34TCL_CULL_FACE_FRONT_AND_BACK); break; default: - so_data(so, NV40TCL_CULL_FACE_BACK); + so_data(so, NV34TCL_CULL_FACE_BACK); break; } - so_data(so, NV40TCL_FRONT_FACE_CCW); + so_data(so, NV34TCL_FRONT_FACE_CCW); } else { so_data(so, nvgl_polygon_mode(cso->fill_cw)); so_data(so, nvgl_polygon_mode(cso->fill_ccw)); switch (cso->cull_mode) { case PIPE_WINDING_CCW: - so_data(so, NV40TCL_CULL_FACE_BACK); + so_data(so, NV34TCL_CULL_FACE_BACK); break; case PIPE_WINDING_CW: - so_data(so, NV40TCL_CULL_FACE_FRONT); + so_data(so, NV34TCL_CULL_FACE_FRONT); break; case PIPE_WINDING_BOTH: - so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK); + so_data(so, NV34TCL_CULL_FACE_FRONT_AND_BACK); break; default: - so_data(so, NV40TCL_CULL_FACE_BACK); + so_data(so, NV34TCL_CULL_FACE_BACK); break; } - so_data(so, NV40TCL_FRONT_FACE_CW); + so_data(so, NV34TCL_FRONT_FACE_CW); } so_data(so, cso->poly_smooth ? 1 : 0); so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0); - so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1); + so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); so_data (so, cso->poly_stipple_enable ? 1 : 0); - so_method(so, curie, NV40TCL_POLYGON_OFFSET_POINT_ENABLE, 3); + so_method(so, curie, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3); if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) || (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT)) so_data(so, 1); @@ -395,12 +395,12 @@ nv40_rasterizer_state_create(struct pipe_context *pipe, else so_data(so, 0); if (cso->offset_cw || cso->offset_ccw) { - so_method(so, curie, NV40TCL_POLYGON_OFFSET_FACTOR, 2); + so_method(so, curie, NV34TCL_POLYGON_OFFSET_FACTOR, 2); so_data (so, fui(cso->offset_scale)); so_data (so, fui(cso->offset_units * 2)); } - so_method(so, curie, NV40TCL_POINT_SPRITE, 1); + so_method(so, curie, NV34TCL_POINT_SPRITE, 1); if (cso->point_quad_rasterization) { unsigned psctl = (1 << 0), i; @@ -448,43 +448,43 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, struct nouveau_stateobj *so = so_new(6, 20, 0); struct nouveau_grobj *curie = nv40->screen->curie; - so_method(so, curie, NV40TCL_DEPTH_FUNC, 3); + so_method(so, curie, NV34TCL_DEPTH_FUNC, 3); so_data (so, nvgl_comparison_op(cso->depth.func)); so_data (so, cso->depth.writemask ? 1 : 0); so_data (so, cso->depth.enabled ? 1 : 0); - so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3); + so_method(so, curie, NV34TCL_ALPHA_FUNC_ENABLE, 3); so_data (so, cso->alpha.enabled ? 1 : 0); so_data (so, nvgl_comparison_op(cso->alpha.func)); so_data (so, float_to_ubyte(cso->alpha.ref_value)); if (cso->stencil[0].enabled) { - so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 3); + so_method(so, curie, NV34TCL_STENCIL_FRONT_ENABLE, 3); so_data (so, cso->stencil[0].enabled ? 1 : 0); so_data (so, cso->stencil[0].writemask); so_data (so, nvgl_comparison_op(cso->stencil[0].func)); - so_method(so, curie, NV40TCL_STENCIL_FRONT_FUNC_MASK, 4); + so_method(so, curie, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4); so_data (so, cso->stencil[0].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); } else { - so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 1); + so_method(so, curie, NV34TCL_STENCIL_FRONT_ENABLE, 1); so_data (so, 0); } if (cso->stencil[1].enabled) { - so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 3); + so_method(so, curie, NV34TCL_STENCIL_BACK_ENABLE, 3); so_data (so, cso->stencil[1].enabled ? 1 : 0); so_data (so, cso->stencil[1].writemask); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); - so_method(so, curie, NV40TCL_STENCIL_BACK_FUNC_MASK, 4); + so_method(so, curie, NV34TCL_STENCIL_BACK_FUNC_MASK, 4); so_data (so, cso->stencil[1].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); } else { - so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 1); + so_method(so, curie, NV34TCL_STENCIL_BACK_ENABLE, 1); so_data (so, 0); } diff --git a/src/gallium/drivers/nv40/nv40_state_blend.c b/src/gallium/drivers/nv40/nv40_state_blend.c index 3ff00a37f66..9da13123aba 100644 --- a/src/gallium/drivers/nv40/nv40_state_blend.c +++ b/src/gallium/drivers/nv40/nv40_state_blend.c @@ -21,7 +21,7 @@ nv40_state_blend_colour_validate(struct nv40_context *nv40) struct nouveau_stateobj *so = so_new(1, 1, 0); struct pipe_blend_color *bcol = &nv40->blend_colour; - so_method(so, nv40->screen->curie, NV40TCL_BLEND_COLOR, 1); + so_method(so, nv40->screen->curie, NV34TCL_BLEND_COLOR, 1); so_data (so, ((float_to_ubyte(bcol->color[3]) << 24) | (float_to_ubyte(bcol->color[0]) << 16) | (float_to_ubyte(bcol->color[1]) << 8) | diff --git a/src/gallium/drivers/nv40/nv40_state_fb.c b/src/gallium/drivers/nv40/nv40_state_fb.c index fd3fdfddc09..93e91b9e3bc 100644 --- a/src/gallium/drivers/nv40/nv40_state_fb.c +++ b/src/gallium/drivers/nv40/nv40_state_fb.c @@ -49,23 +49,23 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) for (i = 1; i < fb->nr_cbufs; i++) assert(!(rt[i]->base.texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)); - rt_format = NV40TCL_RT_FORMAT_TYPE_SWIZZLED | - log2i(fb->width) << NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT | - log2i(fb->height) << NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT; + rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED | + log2i(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT | + log2i(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT; } else - rt_format = NV40TCL_RT_FORMAT_TYPE_LINEAR; + rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR; switch (colour_format) { case PIPE_FORMAT_B8G8R8X8_UNORM: - rt_format |= NV40TCL_RT_FORMAT_COLOR_X8R8G8B8; + rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8; break; case PIPE_FORMAT_B8G8R8A8_UNORM: case 0: - rt_format |= NV40TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8; break; case PIPE_FORMAT_B5G6R5_UNORM: - rt_format |= NV40TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5; break; default: assert(0); @@ -73,23 +73,23 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) switch (zeta_format) { case PIPE_FORMAT_Z16_UNORM: - rt_format |= NV40TCL_RT_FORMAT_ZETA_Z16; + rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16; break; case PIPE_FORMAT_S8Z24_UNORM: case PIPE_FORMAT_X8Z24_UNORM: case 0: - rt_format |= NV40TCL_RT_FORMAT_ZETA_Z24S8; + rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8; break; default: assert(0); } if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) { - so_method(so, curie, NV40TCL_DMA_COLOR0, 1); + so_method(so, curie, NV34TCL_DMA_COLOR0, 1); so_reloc (so, nv40_surface_buffer(&rt[0]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV40TCL_COLOR0_PITCH, 2); + so_method(so, curie, NV34TCL_COLOR0_PITCH, 2); so_data (so, rt[0]->pitch); so_reloc (so, nv40_surface_buffer(&rt[0]->base), rt[0]->base.offset, rt_flags | NOUVEAU_BO_LOW, @@ -97,11 +97,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) } if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) { - so_method(so, curie, NV40TCL_DMA_COLOR1, 1); + so_method(so, curie, NV34TCL_DMA_COLOR1, 1); so_reloc (so, nv40_surface_buffer(&rt[1]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV40TCL_COLOR1_OFFSET, 2); + so_method(so, curie, NV34TCL_COLOR1_OFFSET, 2); so_reloc (so, nv40_surface_buffer(&rt[1]->base), rt[1]->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); @@ -135,11 +135,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) } if (zeta_format) { - so_method(so, curie, NV40TCL_DMA_ZETA, 1); + so_method(so, curie, NV34TCL_DMA_ZETA, 1); so_reloc (so, nv40_surface_buffer(&zeta->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV40TCL_ZETA_OFFSET, 1); + so_method(so, curie, NV34TCL_ZETA_OFFSET, 1); so_reloc (so, nv40_surface_buffer(&zeta->base), zeta->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); so_method(so, curie, NV40TCL_ZETA_PITCH, 1); @@ -148,14 +148,14 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) so_method(so, curie, NV40TCL_RT_ENABLE, 1); so_data (so, rt_enable); - so_method(so, curie, NV40TCL_RT_HORIZ, 3); + so_method(so, curie, NV34TCL_RT_HORIZ, 3); so_data (so, (w << 16) | 0); so_data (so, (h << 16) | 0); so_data (so, rt_format); - so_method(so, curie, NV40TCL_VIEWPORT_HORIZ, 2); + so_method(so, curie, NV34TCL_VIEWPORT_HORIZ, 2); so_data (so, (w << 16) | 0); so_data (so, (h << 16) | 0); - so_method(so, curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2); + so_method(so, curie, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2); so_data (so, ((w - 1) << 16) | 0); so_data (so, ((h - 1) << 16) | 0); so_method(so, curie, 0x1d88, 1); diff --git a/src/gallium/drivers/nv40/nv40_state_scissor.c b/src/gallium/drivers/nv40/nv40_state_scissor.c index 753a505e934..91bff4849c9 100644 --- a/src/gallium/drivers/nv40/nv40_state_scissor.c +++ b/src/gallium/drivers/nv40/nv40_state_scissor.c @@ -13,7 +13,7 @@ nv40_state_scissor_validate(struct nv40_context *nv40) nv40->state.scissor_enabled = rast->scissor; so = so_new(1, 2, 0); - so_method(so, nv40->screen->curie, NV40TCL_SCISSOR_HORIZ, 2); + so_method(so, nv40->screen->curie, NV34TCL_SCISSOR_HORIZ, 2); if (nv40->state.scissor_enabled) { so_data (so, ((s->maxx - s->minx) << 16) | s->minx); so_data (so, ((s->maxy - s->miny) << 16) | s->miny); diff --git a/src/gallium/drivers/nv40/nv40_state_stipple.c b/src/gallium/drivers/nv40/nv40_state_stipple.c index 2b371ebfec0..ed8643b9c19 100644 --- a/src/gallium/drivers/nv40/nv40_state_stipple.c +++ b/src/gallium/drivers/nv40/nv40_state_stipple.c @@ -15,14 +15,14 @@ nv40_state_stipple_validate(struct nv40_context *nv40) unsigned i; so = so_new(2, 33, 0); - so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1); + so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); so_data (so, 1); - so_method(so, curie, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 32); + so_method(so, curie, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32); for (i = 0; i < 32; i++) so_data(so, nv40->stipple[i]); } else { so = so_new(1, 1, 0); - so_method(so, curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1); + so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1); so_data (so, 0); } diff --git a/src/gallium/drivers/nv40/nv40_state_viewport.c b/src/gallium/drivers/nv40/nv40_state_viewport.c index 3aacb00f996..3a5ea0e4807 100644 --- a/src/gallium/drivers/nv40/nv40_state_viewport.c +++ b/src/gallium/drivers/nv40/nv40_state_viewport.c @@ -12,7 +12,7 @@ nv40_state_viewport_validate(struct nv40_context *nv40) so = so_new(2, 9, 0); so_method(so, nv40->screen->curie, - NV40TCL_VIEWPORT_TRANSLATE_X, 8); + NV34TCL_VIEWPORT_TRANSLATE_X, 8); so_data (so, fui(vpt->translate[0])); so_data (so, fui(vpt->translate[1])); so_data (so, fui(vpt->translate[2])); diff --git a/src/gallium/drivers/nv40/nv40_state_zsa.c b/src/gallium/drivers/nv40/nv40_state_zsa.c index 9cbe7da6db1..bf68c60ace5 100644 --- a/src/gallium/drivers/nv40/nv40_state_zsa.c +++ b/src/gallium/drivers/nv40/nv40_state_zsa.c @@ -22,9 +22,9 @@ nv40_state_sr_validate(struct nv40_context *nv40) struct nouveau_stateobj *so = so_new(2, 2, 0); struct pipe_stencil_ref *sr = &nv40->stencil_ref; - so_method(so, nv40->screen->curie, NV40TCL_STENCIL_FRONT_FUNC_REF, 1); + so_method(so, nv40->screen->curie, NV34TCL_STENCIL_FRONT_FUNC_REF, 1); so_data (so, sr->ref_value[0]); - so_method(so, nv40->screen->curie, NV40TCL_STENCIL_BACK_FUNC_REF, 1); + so_method(so, nv40->screen->curie, NV34TCL_STENCIL_BACK_FUNC_REF, 1); so_data (so, sr->ref_value[1]); so_ref(so, &nv40->state.hw[NV40_STATE_SR]); diff --git a/src/gallium/drivers/nv40/nv40_vbo.c b/src/gallium/drivers/nv40/nv40_vbo.c index fabdf4bf23b..a2f06ead86d 100644 --- a/src/gallium/drivers/nv40/nv40_vbo.c +++ b/src/gallium/drivers/nv40/nv40_vbo.c @@ -20,19 +20,19 @@ nv40_vbo_format_to_hw(enum pipe_format pipe, unsigned *fmt, unsigned *ncomp) case PIPE_FORMAT_R32G32_FLOAT: case PIPE_FORMAT_R32G32B32_FLOAT: case PIPE_FORMAT_R32G32B32A32_FLOAT: - *fmt = NV40TCL_VTXFMT_TYPE_FLOAT; + *fmt = NV34TCL_VTXFMT_TYPE_FLOAT; break; case PIPE_FORMAT_R8_UNORM: case PIPE_FORMAT_R8G8_UNORM: case PIPE_FORMAT_R8G8B8_UNORM: case PIPE_FORMAT_R8G8B8A8_UNORM: - *fmt = NV40TCL_VTXFMT_TYPE_UBYTE; + *fmt = NV34TCL_VTXFMT_TYPE_UBYTE; break; case PIPE_FORMAT_R16_SSCALED: case PIPE_FORMAT_R16G16_SSCALED: case PIPE_FORMAT_R16G16B16_SSCALED: case PIPE_FORMAT_R16G16B16A16_SSCALED: - *fmt = NV40TCL_VTXFMT_TYPE_USHORT; + *fmt = NV34TCL_VTXFMT_TYPE_USHORT; break; default: NOUVEAU_ERR("Unknown format %s\n", util_format_name(pipe)); @@ -86,10 +86,10 @@ nv40_vbo_set_idxbuf(struct nv40_context *nv40, struct pipe_buffer *ib, switch (ib_size) { case 2: - type = NV40TCL_IDXBUF_FORMAT_TYPE_U16; + type = NV34TCL_IDXBUF_FORMAT_TYPE_U16; break; case 4: - type = NV40TCL_IDXBUF_FORMAT_TYPE_U32; + type = NV34TCL_IDXBUF_FORMAT_TYPE_U32; break; default: return FALSE; @@ -122,31 +122,31 @@ nv40_vbo_static_attrib(struct nv40_context *nv40, struct nouveau_stateobj *so, map += vb->buffer_offset + ve->src_offset; switch (type) { - case NV40TCL_VTXFMT_TYPE_FLOAT: + case NV34TCL_VTXFMT_TYPE_FLOAT: { float *v = map; switch (ncomp) { case 4: - so_method(so, curie, NV40TCL_VTX_ATTR_4F_X(attrib), 4); + so_method(so, curie, NV34TCL_VTX_ATTR_4F_X(attrib), 4); so_data (so, fui(v[0])); so_data (so, fui(v[1])); so_data (so, fui(v[2])); so_data (so, fui(v[3])); break; case 3: - so_method(so, curie, NV40TCL_VTX_ATTR_3F_X(attrib), 3); + so_method(so, curie, NV34TCL_VTX_ATTR_3F_X(attrib), 3); so_data (so, fui(v[0])); so_data (so, fui(v[1])); so_data (so, fui(v[2])); break; case 2: - so_method(so, curie, NV40TCL_VTX_ATTR_2F_X(attrib), 2); + so_method(so, curie, NV34TCL_VTX_ATTR_2F_X(attrib), 2); so_data (so, fui(v[0])); so_data (so, fui(v[1])); break; case 1: - so_method(so, curie, NV40TCL_VTX_ATTR_1F(attrib), 1); + so_method(so, curie, NV34TCL_VTX_ATTR_1F(attrib), 1); so_data (so, fui(v[0])); break; default: @@ -194,12 +194,12 @@ nv40_draw_arrays(struct pipe_context *pipe, continue; } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, nvgl_primitive(mode)); nr = (vc & 0xff); if (nr) { - BEGIN_RING(chan, curie, NV40TCL_VB_VERTEX_BATCH, 1); + BEGIN_RING(chan, curie, NV34TCL_VB_VERTEX_BATCH, 1); OUT_RING (chan, ((nr - 1) << 24) | start); start += nr; } @@ -210,14 +210,14 @@ nv40_draw_arrays(struct pipe_context *pipe, nr -= push; - BEGIN_RING_NI(chan, curie, NV40TCL_VB_VERTEX_BATCH, push); + BEGIN_RING_NI(chan, curie, NV34TCL_VB_VERTEX_BATCH, push); while (push--) { OUT_RING(chan, ((0x100 - 1) << 24) | start); start += 0x100; } } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, 0); count -= vc; @@ -249,11 +249,11 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib, } count -= vc; - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, nvgl_primitive(mode)); if (vc & 1) { - BEGIN_RING(chan, curie, NV40TCL_VB_ELEMENT_U32, 1); + BEGIN_RING(chan, curie, NV34TCL_VB_ELEMENT_U32, 1); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -263,7 +263,7 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib, push = MIN2(vc, 2047 * 2); - BEGIN_RING_NI(chan, curie, NV40TCL_VB_ELEMENT_U16, push >> 1); + BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U16, push >> 1); for (i = 0; i < push; i+=2) OUT_RING(chan, (elts[i+1] << 16) | elts[i]); @@ -271,7 +271,7 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib, elts += push; } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, 0); start = restart; @@ -300,11 +300,11 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib, } count -= vc; - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, nvgl_primitive(mode)); if (vc & 1) { - BEGIN_RING(chan, curie, NV40TCL_VB_ELEMENT_U32, 1); + BEGIN_RING(chan, curie, NV34TCL_VB_ELEMENT_U32, 1); OUT_RING (chan, elts[0]); elts++; vc--; } @@ -314,7 +314,7 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib, push = MIN2(vc, 2047 * 2); - BEGIN_RING_NI(chan, curie, NV40TCL_VB_ELEMENT_U16, push >> 1); + BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U16, push >> 1); for (i = 0; i < push; i+=2) OUT_RING(chan, (elts[i+1] << 16) | elts[i]); @@ -322,7 +322,7 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib, elts += push; } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, 0); start = restart; @@ -351,20 +351,20 @@ nv40_draw_elements_u32(struct nv40_context *nv40, void *ib, } count -= vc; - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, nvgl_primitive(mode)); while (vc) { push = MIN2(vc, 2047); - BEGIN_RING_NI(chan, curie, NV40TCL_VB_ELEMENT_U32, push); + BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U32, push); OUT_RINGp (chan, elts, push); vc -= push; elts += push; } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, 0); start = restart; @@ -426,12 +426,12 @@ nv40_draw_elements_vbo(struct pipe_context *pipe, continue; } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, nvgl_primitive(mode)); nr = (vc & 0xff); if (nr) { - BEGIN_RING(chan, curie, NV40TCL_VB_INDEX_BATCH, 1); + BEGIN_RING(chan, curie, NV34TCL_VB_INDEX_BATCH, 1); OUT_RING (chan, ((nr - 1) << 24) | start); start += nr; } @@ -442,14 +442,14 @@ nv40_draw_elements_vbo(struct pipe_context *pipe, nr -= push; - BEGIN_RING_NI(chan, curie, NV40TCL_VB_INDEX_BATCH, push); + BEGIN_RING_NI(chan, curie, NV34TCL_VB_INDEX_BATCH, push); while (push--) { OUT_RING(chan, ((0x100 - 1) << 24) | start); start += 0x100; } } - BEGIN_RING(chan, curie, NV40TCL_BEGIN_END, 1); + BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1); OUT_RING (chan, 0); count -= vc; @@ -493,9 +493,9 @@ nv40_vbo_validate(struct nv40_context *nv40) int hw; vtxbuf = so_new(3, 17, 18); - so_method(vtxbuf, curie, NV40TCL_VTXBUF_ADDRESS(0), nv40->vtxelt->num_elements); + so_method(vtxbuf, curie, NV34TCL_VTXBUF_ADDRESS(0), nv40->vtxelt->num_elements); vtxfmt = so_new(1, 16, 0); - so_method(vtxfmt, curie, NV40TCL_VTXFMT(0), nv40->vtxelt->num_elements); + so_method(vtxfmt, curie, NV34TCL_VTXFMT(0), nv40->vtxelt->num_elements); for (hw = 0; hw < nv40->vtxelt->num_elements; hw++) { struct pipe_vertex_element *ve; @@ -511,7 +511,7 @@ nv40_vbo_validate(struct nv40_context *nv40) if (nv40_vbo_static_attrib(nv40, sattr, hw, ve, vb)) { so_data(vtxbuf, 0); - so_data(vtxfmt, NV40TCL_VTXFMT_TYPE_FLOAT); + so_data(vtxfmt, NV34TCL_VTXFMT_TYPE_FLOAT); continue; } } @@ -526,18 +526,18 @@ nv40_vbo_validate(struct nv40_context *nv40) so_reloc(vtxbuf, nouveau_bo(vb->buffer), vb->buffer_offset + ve->src_offset, vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 0, NV40TCL_VTXBUF_ADDRESS_DMA1); - so_data (vtxfmt, ((vb->stride << NV40TCL_VTXFMT_STRIDE_SHIFT) | - (ncomp << NV40TCL_VTXFMT_SIZE_SHIFT) | type)); + 0, NV34TCL_VTXBUF_ADDRESS_DMA1); + so_data (vtxfmt, ((vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT) | + (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type)); } if (ib) { struct nouveau_bo *bo = nouveau_bo(ib); - so_method(vtxbuf, curie, NV40TCL_IDXBUF_ADDRESS, 2); + so_method(vtxbuf, curie, NV34TCL_IDXBUF_ADDRESS, 2); so_reloc (vtxbuf, bo, 0, vb_flags | NOUVEAU_BO_LOW, 0, 0); so_reloc (vtxbuf, bo, ib_format, vb_flags | NOUVEAU_BO_OR, - 0, NV40TCL_IDXBUF_FORMAT_DMA1); + 0, NV34TCL_IDXBUF_FORMAT_DMA1); } so_method(vtxbuf, curie, 0x1710, 1); diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c b/src/gallium/drivers/nv40/nv40_vertprog.c index c93c5d127c4..2abda14f313 100644 --- a/src/gallium/drivers/nv40/nv40_vertprog.c +++ b/src/gallium/drivers/nv40/nv40_vertprog.c @@ -207,32 +207,32 @@ emit_dst(struct nv40_vpc *vpc, uint32_t *hw, int slot, struct nv40_sreg dst) case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break; case NV40_VP_INST_DEST_CLIP(0): vp->or |= (1 << 6); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE0; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0; dst.index = NV40_VP_INST_DEST_FOGC; break; case NV40_VP_INST_DEST_CLIP(1): vp->or |= (1 << 7); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE1; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1; dst.index = NV40_VP_INST_DEST_FOGC; break; case NV40_VP_INST_DEST_CLIP(2): vp->or |= (1 << 8); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE2; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2; dst.index = NV40_VP_INST_DEST_FOGC; break; case NV40_VP_INST_DEST_CLIP(3): vp->or |= (1 << 9); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE3; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3; dst.index = NV40_VP_INST_DEST_PSZ; break; case NV40_VP_INST_DEST_CLIP(4): vp->or |= (1 << 10); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE4; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4; dst.index = NV40_VP_INST_DEST_PSZ; break; case NV40_VP_INST_DEST_CLIP(5): vp->or |= (1 << 11); - vp->clip_ctrl |= NV40TCL_CLIP_PLANE_ENABLE_PLANE5; + vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5; dst.index = NV40_VP_INST_DEST_PSZ; break; default: @@ -887,12 +887,12 @@ check_gpu_resources: } so = so_new(3, 4, 0); - so_method(so, curie, NV40TCL_VP_START_FROM_ID, 1); + so_method(so, curie, NV34TCL_VP_START_FROM_ID, 1); so_data (so, vp->exec->start); so_method(so, curie, NV40TCL_VP_ATTRIB_EN, 2); so_data (so, vp->ir); so_data (so, vp->or); - so_method(so, curie, NV40TCL_CLIP_PLANE_ENABLE, 1); + so_method(so, curie, NV34TCL_VP_CLIP_PLANES_ENABLE, 1); so_data (so, vp->clip_ctrl); so_ref(so, &vp->so); so_ref(NULL, &so); @@ -976,7 +976,7 @@ check_gpu_resources: 4 * sizeof(float)); } - BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_CONST_ID, 5); + BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_CONST_ID, 5); OUT_RING (chan, i + vp->data->start); OUT_RINGp (chan, (uint32_t *)vpd->value, 4); } @@ -995,10 +995,10 @@ check_gpu_resources: NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]); } #endif - BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_FROM_ID, 1); + BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_FROM_ID, 1); OUT_RING (chan, vp->exec->start); for (i = 0; i < vp->nr_insns; i++) { - BEGIN_RING(chan, curie, NV40TCL_VP_UPLOAD_INST(0), 4); + BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_INST(0), 4); OUT_RINGp (chan, vp->insns[i].data, 4); } } -- 2.30.2