From 5f79875266bb30f210a53d2b181ba55b198cfe0d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 17:51:19 +0100 Subject: [PATCH] add SPBlock_512W64B8W.v to sources --- Makefile | 2 ++ SPBlock_512W64B8W.v => libresoc/SPBlock_512W64B8W.v | 0 libresoc/core.py | 1 + 3 files changed, 3 insertions(+) rename SPBlock_512W64B8W.v => libresoc/SPBlock_512W64B8W.v (100%) diff --git a/Makefile b/Makefile index a235508..1bfeeb3 100644 --- a/Makefile +++ b/Makefile @@ -4,6 +4,7 @@ ls1804k: cp build/ls180sram4k/gateware/mem.init . cp build/ls180sram4k/gateware/mem_1.init . cp libresoc/libresoc.v . + cp libresoc/SPBlock_512W64B8W.v . yosys -p 'read_verilog libresoc.v' \ -p 'write_ilang libresoc_cvt.il' yosys -p 'read_verilog ls180.v' \ @@ -19,6 +20,7 @@ ls180: cp build/ls180/gateware/mem.init . cp build/ls180/gateware/mem_1.init . cp libresoc/libresoc.v . + cp libresoc/SPBlock_512W64B8W.v . yosys -p 'read_verilog libresoc.v' \ -p 'read_verilog ls180.v' \ -p 'proc' \ diff --git a/SPBlock_512W64B8W.v b/libresoc/SPBlock_512W64B8W.v similarity index 100% rename from SPBlock_512W64B8W.v rename to libresoc/SPBlock_512W64B8W.v diff --git a/libresoc/core.py b/libresoc/core.py index 66f3eb2..0146511 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -368,6 +368,7 @@ class LibreSoC(CPU): def add_sources(platform): cdir = os.path.dirname(__file__) platform.add_source(os.path.join(cdir, "libresoc.v")) + platform.add_source(os.path.join(cdir, "SPBlock_512W64B8W.v")) def do_finalize(self): self.specials += Instance("test_issuer", **self.cpu_params) -- 2.30.2