From 5fb6ce6983e7e16d2b207f4a1e4ee35bbf90c6f8 Mon Sep 17 00:00:00 2001
From: Tobias Platen <tplaten@posteo.de>
Date: Wed, 13 Apr 2022 19:28:42 +0200
Subject: [PATCH] begin working on linux verilator simulation

---
 Makefile | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index b99adf0..dd546e8 100644
--- a/Makefile
+++ b/Makefile
@@ -147,7 +147,7 @@ $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_f
 endif
 
 # Hello world - working using libre-soc core
-MEMORY_SIZE ?=8192
+#MEMORY_SIZE ?=8192
 RAM_INIT_FILE ?=hello_world/hello_world.hex
 
 # Micropython
@@ -155,11 +155,11 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex
 #RAM_INIT_FILE=micropython/firmware.hex
 
 # Linux
-#MEMORY_SIZE=536870912
+MEMORY_SIZE=536870912
 #RAM_INIT_FILE=dtbImage.microwatt.hex
-#SIM_MAIN_BRAM=false
-#SIM_BRAM_CHAINBOOT=6291456 # 0x600000
-#SIM_MAIN_BRAM=false
+SIM_MAIN_BRAM=false
+SIM_BRAM_CHAINBOOT=6291456 # 0x600000
+
 
 
 FPGA_TARGET ?= ORANGE-CRAB-0.21
-- 
2.30.2