From 5fd7f0ef97e364f6ab7111c31b3d895d0c339495 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Nov 2018 23:23:13 +0000
Subject: [PATCH] add predication remap option

---
 riscv/processor.cc        |  7 +++++--
 riscv/processor.h         |  2 +-
 riscv/sv.cc               | 13 ++++++-------
 riscv/sv.h                |  4 ++++
 riscv/sv_decode.h         |  2 +-
 riscv/sv_insn_redirect.cc |  4 ++--
 riscv/sv_insn_redirect.h  |  2 +-
 7 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 773fab8..f84aa8f 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -193,13 +193,13 @@ sv_csr_t &state_t::sv()
     return get_usv();
 }
 
-sv_shape_t* state_t::get_shape(reg_t reg)
+sv_shape_t* state_t::get_shape(reg_t reg, bool pred)
 {
     if (prv == PRV_M || prv == PRV_S || reg == 0) {
         return NULL;
     }
     for (int i = 0; i < 3; i++) {
-        if (remap[i].regidx == reg) {
+        if (remap[i].regidx == reg && remap[i].pred == pred) {
             return &shape[i];
         }
     }
@@ -614,6 +614,9 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       state.remap[0].regidx = get_field(val, SV_REMAP_REGIDX0);
       state.remap[1].regidx = get_field(val, SV_REMAP_REGIDX1);
       state.remap[2].regidx = get_field(val, SV_REMAP_REGIDX2);
+      state.remap[0].pred = get_field(val, SV_REMAP_PRED0);
+      state.remap[1].pred = get_field(val, SV_REMAP_PRED1);
+      state.remap[2].pred = get_field(val, SV_REMAP_PRED2);
       state.remap[0].shape = get_field(val, SV_REMAP_SHAPE0);
       state.remap[1].shape = get_field(val, SV_REMAP_SHAPE1);
       state.remap[2].shape = get_field(val, SV_REMAP_SHAPE2);
diff --git a/riscv/processor.h b/riscv/processor.h
index 4a7fee8..efd8945 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -168,7 +168,7 @@ struct state_t
   sv_remap_t remap[3];
   sv_shape_t shape[3];
 
-  sv_shape_t *get_shape(reg_t reg);
+  sv_shape_t *get_shape(reg_t reg, bool pred=false);
   void sv_csr_reg_unpack();
   void sv_csr_pred_unpack();
   void get_csr_start_end(int &start, int &end);
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 2096351..8f24631 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -277,15 +277,14 @@ uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs)
 }
 
 // for use in predicated branches. sets bit N if val=true; clears bit N if false
-uint64_t sv_insn_t::rd_bitset(reg_t reg, uint64_t bit, bool set)
+uint64_t sv_insn_t::rd_bitset(reg_t reg, int bit, bool set)
 {
-    //reg_spec_t rs = {reg, NULL};
-    //uint64_t val = p->s.READ_REG(rs);
+    reg_spec_t rs = {reg, &bit};
     uint64_t val = STATE.XPR[reg];
     if (set) {
-        val |= (1<<bit);
+        val |= (1UL<<bit);
     } else {
-        val &= ~(1<<bit);
+        val &= ~(1UL<<bit);
     }
     STATE.XPR.write(reg, val);
     return val;
@@ -377,11 +376,11 @@ uint64_t sv_csr_t::regpush(uint16_t csrval, int len, bool top)
                 fprintf(stderr, "regcsr shuffle %d %d\n", idx, idx+1);
             }
             sv_csrs[topstack].u = csrval;
-            fprintf(stderr, "regcsr set %d %lx\n", topstack, csrval);
+            fprintf(stderr, "regcsr set %d %x\n", topstack, csrval);
             return popped;
         } else {
             sv_csrs[topstack].u = csrval;
-            fprintf(stderr, "regcsr set %d %lx\n", topstack, csrval);
+            fprintf(stderr, "regcsr set %d %x\n", topstack, csrval);
             return 0;
         }
     }
diff --git a/riscv/sv.h b/riscv/sv.h
index d5db778..3df72d2 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -74,6 +74,7 @@ bool sv_check_reg(bool intreg, uint64_t reg);
 typedef struct {
     uint64_t regidx: 7; // actual i.e. real register (0-127)
     unsigned int shape: 2; // which shape register to use
+    bool pred;
 } sv_remap_t;
 
 typedef struct {
@@ -87,8 +88,11 @@ typedef struct {
 } sv_shape_t;
 
 #define SV_REMAP_REGIDX0 (0x7f)
+#define SV_REMAP_PRED0 (0x80)
 #define SV_REMAP_REGIDX1 (0x7f<<8)
+#define SV_REMAP_PRED1 (0x800)
 #define SV_REMAP_REGIDX2 (0x7f<<16)
+#define SV_REMAP_PRED2 (0x8000)
 #define SV_REMAP_SHAPE0 (0x3<<24)
 #define SV_REMAP_SHAPE1 (0x3<<26)
 #define SV_REMAP_SHAPE2 (0x3<<28)
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 18f67ae..0727487 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -91,7 +91,7 @@ public:
              reg_t *target_reg);
 
   // used for predicated branches. sets bit N if val=true; clears bit N if false
-  uint64_t rd_bitset(reg_t reg, uint64_t bit, bool val);
+  uint64_t rd_bitset(reg_t reg, int bit, bool val);
 
   bool sv_check_reg(bool intreg, uint64_t reg);
   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 7905245..14a9d65 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -121,10 +121,10 @@ union freg_shift {
     uint8_t b[sizeof(freg_t)*8];
 };
 
-unsigned int sv_proc_t::remap(reg_spec_t const& spec)
+unsigned int sv_proc_t::remap(reg_spec_t const& spec, bool pred)
 {
     unsigned int offs = *spec.offset;
-    sv_shape_t *shape = p->get_state()->get_shape(spec.reg);
+    sv_shape_t *shape = p->get_state()->get_shape(spec.reg, pred);
     if (shape == NULL) {
         return offs;
     }
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index c90eb67..e510b4e 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -265,7 +265,7 @@ public:
     sv_reg_t to_uint32(sv_freg_t const& reg);
     sv_reg_t to_uint32(sv_float32_t const& reg);
 
-    unsigned int remap(reg_spec_t const& regspec);
+    unsigned int remap(reg_spec_t const& regspec, bool pred=false);
 
     bool rv_int_op_prepare(sv_reg_t const & lhs, sv_reg_t const & rhs,
                            uint64_t &vlhs, uint64_t &vrhs,
-- 
2.30.2