From 5fdbf4e82cdea3c99547dcdb4acd4e50118c0527 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 21 Jul 2018 10:01:46 +0100
Subject: [PATCH] add beginnings of eint

---
 src/bsv/bsv_lib/slow_peripherals_template.bsv |  7 ---
 src/bsv/peripheral_gen.py                     | 46 +++++++++++++++++++
 2 files changed, 46 insertions(+), 7 deletions(-)

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 17e724c..7afd7ac 100644
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -103,7 +103,6 @@ package slow_peripherals;
 			Ifc_AxiExpansion		axiexp1			<- mkAxiExpansion();	
 		`endif
     Ifc_pinmux pinmux <- mkpinmux; // mandatory
-    Wire#(Bit#(32)) wr_interrupt <- mkWire();
 		/*=======================================================*/
 
    	AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
@@ -133,12 +132,6 @@ package slow_peripherals;
     /*========== pinmux connections ============*/
 {7}
 {8}
-    for(Integer i=0;i<32;i=i+ 1)begin
-      rule connect_int_to_plic(wr_interrupt[i]==1);
-				ff_gateway_queue[i].enq(1);
-				plic.ifc_external_irq[i].irq_frm_gateway(True);
-      endrule
-    end
     rule rl_completion_msg_from_plic;
 		  let id <- plic.intrpt_completion;
       interrupt_id <= id;
diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 6c49f5f..5560f0f 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -9,6 +9,12 @@ class PBase(object):
     def slowifdeclmux(self):
         return ''
 
+    def slowimport(self):
+        return ''
+
+    def num_axi_regs32(self):
+        return 0
+
     def slowifdecl(self):
         return ''
 
@@ -23,6 +29,8 @@ class PBase(object):
     def axi_reg_def(self, start, name, ifacenum):
         name = name.upper()
         offs = self.num_axi_regs32() * 4 * 16
+        if offs == 0:
+            return ('', 0)
         end = start + offs - 1
         bname = self.axibase(name, ifacenum)
         bend = self.axiend(name, ifacenum)
@@ -264,6 +272,43 @@ class twi(PBase):
         return txt
 
 
+class eint(PBase):
+
+    def mkslow_peripheral(self, size=0):
+        size = len(self.peripheral.pinspecs)
+        return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
+
+
+    def _pinname_out(self, pname):
+        return {'sda': 'out.sda_out',
+                'scl': 'out.scl_out'}.get(pname, '')
+
+    def _pinname_in(self, pname):
+        return {'sda': 'out.sda_in',
+                'scl': 'out.scl_in'}.get(pname, '')
+
+    def _pinname_outen(self, pname):
+        return {'sda': 'out.sda_out_en',
+                'scl': 'out.scl_out_en'}.get(pname, '')
+
+    def mk_pincon(self, name, count):
+        size = len(self.peripheral.pinspecs)
+        ret = []
+        ret.append(eint_pincon_template.format(size))
+        return '\n'.join(ret)
+
+
+eint_pincon_template = '''\
+    // TODO: offset i by the number of eints already used
+    for(Integer i=0;i<{0};i=i+ 1)begin
+      rule connect_int_to_plic(wr_interrupt[i]==1);
+                ff_gateway_queue[i].enq(1);
+                plic.ifc_external_irq[i].irq_frm_gateway(True);
+      endrule
+    end
+'''
+
+
 class spi(PBase):
 
     def slowimport(self):
@@ -662,6 +707,7 @@ class PFactory(object):
                      'qspi': qspi,
                      'spi': spi,
                      'pwm': pwm,
+                     'eint': eint,
                      'gpio': gpio
                      }.items():
             if name.startswith(k):
-- 
2.30.2