From 5fe6c52270e7d42fd99fedbd7ab3650d292f260e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 12 Apr 2011 01:42:55 -0700 Subject: [PATCH] [xcc,sim] rvc loads and stores --- riscv/decode.h | 8 ++- riscv/execute.h | 160 +++++++++++++++++++++++++++++++++++++++++++ riscv/insns/c_ld.h | 3 + riscv/insns/c_ldsp.h | 3 + riscv/insns/c_lw.h | 2 + riscv/insns/c_lwsp.h | 2 + riscv/insns/c_sd.h | 3 + riscv/insns/c_sdsp.h | 3 + riscv/insns/c_sw.h | 2 + riscv/insns/c_swsp.h | 2 + 10 files changed, 187 insertions(+), 1 deletion(-) create mode 100644 riscv/insns/c_ld.h create mode 100644 riscv/insns/c_ldsp.h create mode 100644 riscv/insns/c_lw.h create mode 100644 riscv/insns/c_lwsp.h create mode 100644 riscv/insns/c_sd.h create mode 100644 riscv/insns/c_sdsp.h create mode 100644 riscv/insns/c_sw.h create mode 100644 riscv/insns/c_swsp.h diff --git a/riscv/decode.h b/riscv/decode.h index 499181d..af6b57f 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -206,13 +206,19 @@ private: #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3) -#define CRD do_writeback(XPR,(insn.bits >> 5) & 0x1f) +#define CRD do_writeback(XPR, (insn.bits >> 5) & 0x1f) #define CRS1 XPR[(insn.bits >> 10) & 0x1f] #define CRS2 XPR[(insn.bits >> 5) & 0x1f] #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26) +#define CIMM5 ((int32_t)((insn.bits >> 5) & 0x1f) << 27 >> 27) #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22) #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS)) +static const uint8_t rvc_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; +#define CRDS do_writeback(XPR, rvc_regmap[(insn.bits >> 13) & 0x7]) +#define CRS1S XPR[rvc_regmap[(insn.bits >> 10) & 0x7]] +#define CRS2S XPR[rvc_regmap[(insn.bits >> 13) & 0x7]] + // vector stuff #define VL vl diff --git a/riscv/execute.h b/riscv/execute.h index ad21a0b..96aa835 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -180,6 +180,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x4: + { + #include "insns/c_ldsp.h" + break; + } + case 0x5: + { + #include "insns/c_lwsp.h" + break; + } + case 0x6: + { + #include "insns/c_sdsp.h" + break; + } case 0x7: { switch((insn.bits >> 0x7) & 0x7) @@ -201,6 +216,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x8: + { + #include "insns/c_swsp.h" + break; + } + case 0x9: + { + #include "insns/c_ld.h" + break; + } + case 0xa: + { + #include "insns/c_lw.h" + break; + } case 0xb: { switch((insn.bits >> 0x7) & 0x7) @@ -505,6 +535,16 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0xc: + { + #include "insns/c_sd.h" + break; + } + case 0xd: + { + #include "insns/c_sw.h" + break; + } case 0xf: { switch((insn.bits >> 0x7) & 0x7) @@ -886,6 +926,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x24: + { + #include "insns/c_ldsp.h" + break; + } + case 0x25: + { + #include "insns/c_lwsp.h" + break; + } + case 0x26: + { + #include "insns/c_sdsp.h" + break; + } case 0x27: { switch((insn.bits >> 0x7) & 0x7) @@ -907,6 +962,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x28: + { + #include "insns/c_swsp.h" + break; + } + case 0x29: + { + #include "insns/c_ld.h" + break; + } + case 0x2a: + { + #include "insns/c_lw.h" + break; + } case 0x2b: { switch((insn.bits >> 0x7) & 0x7) @@ -1006,6 +1076,16 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x2c: + { + #include "insns/c_sd.h" + break; + } + case 0x2d: + { + #include "insns/c_sw.h" + break; + } case 0x2f: { switch((insn.bits >> 0x7) & 0x7) @@ -1434,6 +1514,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x44: + { + #include "insns/c_ldsp.h" + break; + } + case 0x45: + { + #include "insns/c_lwsp.h" + break; + } + case 0x46: + { + #include "insns/c_sdsp.h" + break; + } case 0x47: { switch((insn.bits >> 0x7) & 0x7) @@ -1465,6 +1560,21 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x48: + { + #include "insns/c_swsp.h" + break; + } + case 0x49: + { + #include "insns/c_ld.h" + break; + } + case 0x4a: + { + #include "insns/c_lw.h" + break; + } case 0x4b: { switch((insn.bits >> 0x7) & 0x7) @@ -1496,6 +1606,16 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x4c: + { + #include "insns/c_sd.h" + break; + } + case 0x4d: + { + #include "insns/c_sw.h" + break; + } case 0x4f: { switch((insn.bits >> 0x7) & 0x7) @@ -2103,11 +2223,41 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x64: + { + #include "insns/c_ldsp.h" + break; + } + case 0x65: + { + #include "insns/c_lwsp.h" + break; + } + case 0x66: + { + #include "insns/c_sdsp.h" + break; + } case 0x67: { #include "insns/j.h" break; } + case 0x68: + { + #include "insns/c_swsp.h" + break; + } + case 0x69: + { + #include "insns/c_ld.h" + break; + } + case 0x6a: + { + #include "insns/c_lw.h" + break; + } case 0x6b: { switch((insn.bits >> 0x7) & 0x7) @@ -2143,6 +2293,16 @@ switch((insn.bits >> 0x0) & 0x7f) } break; } + case 0x6c: + { + #include "insns/c_sd.h" + break; + } + case 0x6d: + { + #include "insns/c_sw.h" + break; + } case 0x6f: { #include "insns/jal.h" diff --git a/riscv/insns/c_ld.h b/riscv/insns/c_ld.h new file mode 100644 index 0000000..f9c07af --- /dev/null +++ b/riscv/insns/c_ld.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRDS = mmu.load_int64(CRS1S+CIMM5*8); diff --git a/riscv/insns/c_ldsp.h b/riscv/insns/c_ldsp.h new file mode 100644 index 0000000..1fbd9bd --- /dev/null +++ b/riscv/insns/c_ldsp.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +CRD = mmu.load_int64(XPR[30]+CIMM6*8); diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h new file mode 100644 index 0000000..4796ab8 --- /dev/null +++ b/riscv/insns/c_lw.h @@ -0,0 +1,2 @@ +require_rvc; +CRDS = mmu.load_int32(CRS1S+CIMM5*4); diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h new file mode 100644 index 0000000..318342a --- /dev/null +++ b/riscv/insns/c_lwsp.h @@ -0,0 +1,2 @@ +require_rvc; +CRD = mmu.load_int32(XPR[30]+CIMM6*4); diff --git a/riscv/insns/c_sd.h b/riscv/insns/c_sd.h new file mode 100644 index 0000000..b2eb456 --- /dev/null +++ b/riscv/insns/c_sd.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +mmu.store_uint64(CRS1S+CIMM5*8, CRS2S); diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h new file mode 100644 index 0000000..ca97d51 --- /dev/null +++ b/riscv/insns/c_sdsp.h @@ -0,0 +1,3 @@ +require_rvc; +require_xpr64; +mmu.store_uint64(XPR[30]+CIMM6*8, CRS2); diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h new file mode 100644 index 0000000..f604adf --- /dev/null +++ b/riscv/insns/c_sw.h @@ -0,0 +1,2 @@ +require_rvc; +mmu.store_uint32(CRS1S+CIMM5*4, CRS2S); diff --git a/riscv/insns/c_swsp.h b/riscv/insns/c_swsp.h new file mode 100644 index 0000000..0508f12 --- /dev/null +++ b/riscv/insns/c_swsp.h @@ -0,0 +1,2 @@ +require_rvc; +mmu.store_uint32(XPR[30]+CIMM6*4, CRS2); -- 2.30.2