From 5fea87cc7902c7c03c0d3c8cf7784cd99db8315d Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 11 Mar 2020 17:48:10 +0800 Subject: [PATCH] RISC-V: Fix testsuite regression due to recent IRA changes. After IRA changes, atomic version will use one more register, but non-atomic still use 2 registers, however this testcase isn't testing for atomic feature, so I decide change the testcase to always use COUNT++ to test. ChangeLog gcc/testsuite/ Kito Cheng * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/riscv/interrupt-2.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 11061adaf18..e2442fba35a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Kito Cheng + + * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. + 2020-03-11 Richard Biener * gcc.dg/torture/20200311-1.c: New testcase. diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-2.c index 9559007e4ae..82e3fb24e81 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-2.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-2.c @@ -8,10 +8,6 @@ foo2 (void) INTERRUPT_FLAG = 0; extern volatile int COUNTER; -#ifdef __riscv_atomic - __atomic_fetch_add (&COUNTER, 1, __ATOMIC_RELAXED); -#else COUNTER++; -#endif } /* { dg-final { scan-assembler-times "s\[wd\]\ta\[0-7\],\[0-9\]+\\(sp\\)" 2 } } */ -- 2.30.2