From 5ffbc7bf976774caf46892268a1d76e5807afb30 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 31 Jan 2021 17:18:18 -0300 Subject: [PATCH] Fix loop test and enable it Make the code correspond to the comments and vice-versa. Due to the branching, this test is useful for ensuring correctness of the interaction between instruction fetch and issue. --- src/soc/simulator/test_sim.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index 2fcd3e6c..1fe38e73 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -414,21 +414,21 @@ class GeneralTestCases(FHDLTestCase): program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK! self.run_tst_program(program, [1, 3]) - @unittest.skip("disable") def test_loop(self): - """in godbolt.org: - register unsigned long i asm ("r12"); + """ + in godbolt.org: + register unsigned long i asm ("r9"); void square(void) { - i = 5; + i = 16; do { i = i - 1; - } while (i != 0); + } while (i != 12); } """ lst = ["addi 9, 0, 0x10", # i = 16 "addi 9,9,-1", # i = i - 1 - "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2 - "bc 2,0,-8" # branch if CR2 "test was != 0" + "cmpi 2,1,9,12", # compare 9 to value 12, store in CR2 + "bc 4,10,-8" # branch if CR2 "test was != 12" ] with Program(lst, bigendian) as program: self.run_tst_program(program, [9], initial_mem={}) -- 2.30.2