From 60a4a90a19e6fade40e33b46c603c5d4e3f83ce4 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 14 Apr 2021 20:22:20 +0200 Subject: [PATCH] update test_caller_radix.py --- src/soc/decoder/isa/test_caller_radix.py | 26 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py index cec96b66..3c1636e2 100644 --- a/src/soc/decoder/isa/test_caller_radix.py +++ b/src/soc/decoder/isa/test_caller_radix.py @@ -31,20 +31,34 @@ testmem = { 0x40000000000300ad, } +prtbl = 0x1000000 + class DecoderTestCase(FHDLTestCase): def test_load_store(self): - lst = ["addi 1, 0, 0x0010", - "addi 2, 0, 0x1234", - "stw 2, 0(1)", - "lwz 3, 0(1)"] + lst = [#"addi 1, 0, 0x1000", + #"addi 2, 0, 0x1234", + #"stw 2, 0(1)", + "lwz 3, 0(1)" + ] with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program) + initial_regs=[0] * 32 + initial_regs[1] = 0x1000 + initial_regs[2] = 0x1234 + sim = self.run_tst_program(program,initial_regs=initial_regs) print(sim.gpr(1)) self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) def run_tst_program(self, prog, initial_regs=[0] * 32): - simulator = run_tst(prog, initial_regs,mmu=True,mem=testmem) + # set up dummy minimal ISACaller + spr = {'DSISR': SelectableInt(0, 64), + 'DAR': SelectableInt(0, 64), + 'PIDR': SelectableInt(0, 64), + 'PRTBL': SelectableInt(prtbl, 64) + } + + simulator = run_tst(prog, initial_regs,mmu=True,mem=testmem, + initial_sprs=spr) simulator.gpr.dump() return simulator -- 2.30.2