From 60cbaaeb9dacd2fc0506118b6edc00408e0a7754 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 17 Jul 2020 16:52:39 +0200 Subject: [PATCH] Reduce delay between wishbone_write --- gram/simulation/simsoctb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index 508a35a..e90c19e 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -196,9 +196,9 @@ module simsoctb; // Write wishbone_write(32'h10000000 >> 2, 32'h12345678); - #10000; + #2000; wishbone_write(32'h10000100 >> 2, 32'h00000000); - #10000; + #2000; wishbone_read(32'h10000000 >> 2, tmp); assert_equal_32(tmp, 32'h12345678); -- 2.30.2