From 60d8fe9216d68aff1b00fdc8bc2e066ea45aac1e Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Sat, 20 Jan 2018 01:28:07 -0800 Subject: [PATCH] i965: Delete completely bogus comment This hasn't been true in 6+ years, if it was even true then. Before we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used to have two compiler backends for WM programs, based on Mesa IR. One handled flow control and was SIMD8-only, while the other was SIMD16 only and didn't handle flow control. Or something like that. Even then, this certainly didn't handle vertex shaders, so "all ... code generation" is a bit strong. --- src/mesa/drivers/dri/i965/brw_wm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 08bacebd571..942fb04a804 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -126,11 +126,6 @@ brw_wm_debug_recompile(struct brw_context *brw, struct gl_program *prog, } } -/** - * All Mesa program -> GPU code generation goes through this function. - * Depending on the instructions used (i.e. flow control instructions) - * we'll use one of two code generators. - */ static bool brw_codegen_wm_prog(struct brw_context *brw, struct brw_program *fp, -- 2.30.2