From 60fb638f9c08e2cf73605fc5a60531215098a82d Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 4 Jan 2017 04:32:48 +0000 Subject: [PATCH] re PR target/78900 (ICE in gcc.target/powerpc/signbit-3.c) [gcc] 2016-12-30 Michael Meissner PR target/78900 * config/rs6000/rs6000.c (rs6000_split_signbit): Change some assertions. Add support for doing the signbit if the IEEE 128-bit floating point value is in a GPR. * config/rs6000/rs6000.md (Fsignbit): Delete. (signbit2_dm): Delete using and just use "wa". Update the length attribute if the value is in a GPR. (signbit2_dm_ext): Add combiner pattern to eliminate the sign or zero extension instruction, since the value is always 0/1. (signbit2_dm2): Delete using . 2017-01-03 Michael Meissner PR target/78953 * config/rs6000/vsx.md (vsx_extract__store_p9): If we are extracting SImode to a GPR register so that we can generate a store, limit the vector to be in a traditional Altivec register for the vextuwrx instruction. [gcc/testsuite] 2017-01-03 Michael Meissner PR target/78953 * gcc.target/powerpc/pr78953.c: New test. From-SVN: r244044 --- gcc/ChangeLog | 20 +++++++++++++++++ gcc/config/rs6000/rs6000.c | 23 ++++++++++--------- gcc/config/rs6000/rs6000.md | 26 +++++++++++++++++----- gcc/config/rs6000/vsx.md | 2 +- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/pr78953.c | 19 ++++++++++++++++ 6 files changed, 77 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78953.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7cf7c98151..3114e02af67 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2016-12-30 Michael Meissner + + PR target/78900 + * config/rs6000/rs6000.c (rs6000_split_signbit): Change some + assertions. Add support for doing the signbit if the IEEE 128-bit + floating point value is in a GPR. + * config/rs6000/rs6000.md (Fsignbit): Delete. + (signbit2_dm): Delete using and just use "wa". + Update the length attribute if the value is in a GPR. + (signbit2_dm_ext): Add combiner pattern to eliminate + the sign or zero extension instruction, since the value is always + 0/1. + (signbit2_dm2): Delete using . + + PR target/78953 + * config/rs6000/vsx.md (vsx_extract__store_p9): If we are + extracting SImode to a GPR register so that we can generate a + store, limit the vector to be in a traditional Altivec register + for the vextuwrx instruction. + 2017-01-03 Ian Lance Taylor * godump.c (go_format_type): Treat ENUMERAL_TYPE like diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a54ab4809a3..a287a2363b3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -25170,9 +25170,7 @@ rs6000_split_signbit (rtx dest, rtx src) rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest); rtx shift_reg = dest_di; - gcc_assert (REG_P (dest)); - gcc_assert (REG_P (src) || MEM_P (src)); - gcc_assert (s_mode == KFmode || s_mode == TFmode); + gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64); if (MEM_P (src)) { @@ -25184,17 +25182,20 @@ rs6000_split_signbit (rtx dest, rtx src) else { - unsigned int r = REGNO (src); + unsigned int r = reg_or_subregno (src); - /* If this is a VSX register, generate the special mfvsrd instruction - to get it in a GPR. Until we support SF and DF modes, that will - always be true. */ - gcc_assert (VSX_REGNO_P (r)); + if (INT_REGNO_P (r)) + shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0)); - if (s_mode == KFmode) - emit_insn (gen_signbitkf2_dm2 (dest_di, src)); else - emit_insn (gen_signbittf2_dm2 (dest_di, src)); + { + /* Generate the special mfvsrd instruction to get it in a GPR. */ + gcc_assert (VSX_REGNO_P (r)); + if (s_mode == KFmode) + emit_insn (gen_signbitkf2_dm2 (dest_di, src)); + else + emit_insn (gen_signbittf2_dm2 (dest_di, src)); + } } emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63))); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3651fa6bce2..7e103b019f0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -518,9 +518,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) -(define_mode_attr Fsignbit [(KF "wa") - (TF "wa")]) - ; Iterator for ISA 3.0 supported floating point types (define_mode_iterator FP_ISA3 [SF DF @@ -4744,7 +4741,7 @@ (define_insn_and_split "signbit2_dm" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (unspec:SI - [(match_operand:SIGNBIT 1 "input_operand" ",m,r")] + [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")] UNSPEC_SIGNBIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" @@ -4754,7 +4751,24 @@ rs6000_split_signbit (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,12") + [(set_attr "length" "8,8,4") + (set_attr "type" "mftgpr,load,integer")]) + +(define_insn_and_split "*signbit2_dm_ext" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") + (any_extend:DI + (unspec:SI + [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")] + UNSPEC_SIGNBIT)))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rs6000_split_signbit (operands[0], operands[1]); + DONE; +} + [(set_attr "length" "8,8,4") (set_attr "type" "mftgpr,load,integer")]) ;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating @@ -4762,7 +4776,7 @@ ;; special pattern to avoid using a normal movdi. (define_insn "signbit2_dm2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "") + (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa") (const_int 0)] UNSPEC_SIGNBIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e3135530f27..6264e6c7206 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2628,7 +2628,7 @@ (define_insn_and_split "*vsx_extract__store_p9" [(set (match_operand: 0 "memory_operand" "=Z,m") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" ",") + (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" ",v") (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))) (clobber (match_scratch: 3 "=,&r")) (clobber (match_scratch:SI 4 "=X,&r"))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3b448dd98f9..cd2a065ec14 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-01-03 Michael Meissner + + PR target/78953 + * gcc.target/powerpc/pr78953.c: New test. + 2017-01-03 Ian Lance Taylor * gcc.misc-tests/godump-1.c: Update for accurate representation of diff --git a/gcc/testsuite/gcc.target/powerpc/pr78953.c b/gcc/testsuite/gcc.target/powerpc/pr78953.c new file mode 100644 index 00000000000..34a3083918d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78953.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ + +#include + +/* PR 78953: mem = vec_extract (V4SI, ) failed if the vector was in a + traditional FPR register. */ + +void +foo (vector int *vp, int *ip) +{ + vector int v = *vp; + __asm__ (" # fpr %x0" : "+d" (v)); + ip[4] = vec_extract (v, 0); +} + +/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */ -- 2.30.2