From 6107b7844ae1c827869b3577c464e235362d84c6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Feb 2015 12:04:51 +0100 Subject: [PATCH] test implementation on all targets and fix issues --- misoclib/soc/sdram.py | 2 +- targets/de0nano.py | 2 +- targets/kc705.py | 3 ++- targets/mlabs_video.py | 3 ++- targets/pipistrello.py | 4 ++-- targets/ppro.py | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 4b948854..c8534329 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -5,7 +5,7 @@ from misoclib.mem.sdram.bus import dfi, lasmibus, wishbone2lasmi from misoclib.mem.sdram import minicon, lasmicon from misoclib.mem.sdram import dfii from misoclib.mem.sdram import memtest -from misoclib.soc import Soc, mem_decoder +from misoclib.soc import SoC, mem_decoder class SDRAMSoC(SoC): csr_map = { diff --git a/targets/de0nano.py b/targets/de0nano.py index 3062cb3c..62e95fab 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -5,7 +5,7 @@ from misoclib.cpu.peripherals import gpio from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy from misoclib.com import uart -from misoclib.soc import SDRAMSoC +from misoclib.soc.sdram import SDRAMSoC class _PLL(Module): def __init__(self, period_in, name, phase_shift, operation_mode): diff --git a/targets/kc705.py b/targets/kc705.py index 532b1365..8498d91f 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -4,7 +4,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import k7ddrphy from misoclib.mem.flash import spiflash -from misoclib.soc import SDRAMSoC, mem_decoder +from misoclib.soc import mem_decoder +from misoclib.soc.sdram import SDRAMSoC from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.com.liteeth.mac import LiteEthMAC diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 8245a938..a32ab88a 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -10,7 +10,8 @@ from misoclib.mem.sdram.phy import s6ddrphy from misoclib.mem.flash import norflash16 from misoclib.cpu.peripherals import gpio from misoclib.video import framebuffer -from misoclib.soc import SDRAMSoC, mem_decoder +from misoclib.soc import mem_decoder +from misoclib.soc.sdram import SDRAMSoC from misoclib.com.liteeth.phy.mii import LiteEthPHYMII from misoclib.com.liteeth.mac import LiteEthMAC diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 8c27d78b..e7bfe9e9 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -5,8 +5,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy -from misoclib.mem.flash import SpiFlash -from misoclib.soc import SDRAMSoC +from misoclib.mem.flash import spiflash +from misoclib.soc.sdram import SDRAMSoC class _CRG(Module): def __init__(self, platform, clk_freq): diff --git a/targets/ppro.py b/targets/ppro.py index e9108344..d1292a9b 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -6,7 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.flash import spiflash -from misoclib.soc import SDRAMSoC +from misoclib.soc.sdram import SDRAMSoC class _CRG(Module): def __init__(self, platform, clk_freq): -- 2.30.2