From 61087329efcfac45de6b69ded33f38c8f8817eef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 12:36:27 -0700
Subject: [PATCH] Fix tribuf test

---
 tests/ice40/tribuf.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
index ef4266959..d1e1b3108 100644
--- a/tests/ice40/tribuf.ys
+++ b/tests/ice40/tribuf.ys
@@ -2,7 +2,7 @@ read_verilog tribuf.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
-- 
2.30.2