From 610ba01e6e88831479c1ccbcc5fbb6e0ca4752be Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 20:49:00 +0000 Subject: [PATCH] fix SVP64Asm Rc=1 assembly --- src/soc/sv/trans/svp64.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 5702deb8..f52de2a0 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -547,8 +547,9 @@ class SVP64Asm: svp64_prefix |= ((svp64_rm>>(23-i))&0b1) << (31-x) # fiinally yield the svp64 prefix and the thingy. v3.0b opcode + rc = '.' if rc_mode else '' yield ".long 0x%x" % svp64_prefix - yield "%s %s" % (v30b_op, ", ".join(v30b_newfields)) + yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields)) print ("new v3.0B fields", v30b_op, v30b_newfields) if __name__ == '__main__': @@ -564,6 +565,7 @@ if __name__ == '__main__': 'sv.extsw./ff=eq 5, 31', 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31', 'sv.extsw./pr=eq 5.v, 31', + 'sv.add. 5.v, 2.v, 1.v', ]) print ("list", list(isa)) csvs = SVP64RM() -- 2.30.2