From 615ccdd3581c6702e259e045380878dd60c56123 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 6 May 2004 09:20:44 +0000 Subject: [PATCH] 5500.md (ir_vr55_store): Set latency to 0. * config/mips/5500.md (ir_vr55_store): Set latency to 0. (ir_vr55_hilo): Split into... (ir_vr55_mfhilo, ir_vr55_mthilo): ...these new reservations. (ir_vr55_imul_si, ir_vr55_imadd): Change latency to 5. (ir_vr55_imul_di): Change latency to 9. Reserve vr55_mac for 4 cycles. Add various multiplication bypasses. * config/mips/mips.c (mips_rtx_costs): Adjust VR5500 costs for integer multiplication. From-SVN: r81557 --- gcc/ChangeLog | 11 ++++++++ gcc/config/mips/5500.md | 60 +++++++++++++++++++++++++++++++++-------- gcc/config/mips/mips.c | 6 ++--- 3 files changed, 63 insertions(+), 14 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 81de182ac06..ebddaf54fd0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2004-05-06 Richard Sandiford + + * config/mips/5500.md (ir_vr55_store): Set latency to 0. + (ir_vr55_hilo): Split into... + (ir_vr55_mfhilo, ir_vr55_mthilo): ...these new reservations. + (ir_vr55_imul_si, ir_vr55_imadd): Change latency to 5. + (ir_vr55_imul_di): Change latency to 9. Reserve vr55_mac for 4 cycles. + Add various multiplication bypasses. + * config/mips/mips.c (mips_rtx_costs): Adjust VR5500 costs for integer + multiplication. + 2004-05-06 Uros Bizjak * config/i386/i386.md (*fscalexf4): Correct insn "mode" diff --git a/gcc/config/mips/5500.md b/gcc/config/mips/5500.md index d912f666ca6..d5344227d0a 100644 --- a/gcc/config/mips/5500.md +++ b/gcc/config/mips/5500.md @@ -31,7 +31,12 @@ (eq_attr "type" "load,fpload,fpidxload")) "vr55_mem") -(define_insn_reservation "ir_vr55_store" 1 +(define_bypass 4 + "ir_vr55_load" + "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, + ir_vr55_idiv_si,ir_vr55_idiv_di") + +(define_insn_reservation "ir_vr55_store" 0 (and (eq_attr "cpu" "r5500") (eq_attr "type" "store,fpstore,fpidxstore")) "vr55_mem") @@ -49,33 +54,66 @@ (eq_attr "type" "xfer")) "vr55_dp0|vr55_dp1") -(define_insn_reservation "ir_vr55_hilo" 2 - (and (eq_attr "cpu" "r5500") - (eq_attr "type" "mthilo,mfhilo")) - "vr55_dp0|vr55_dp1") - (define_insn_reservation "ir_vr55_arith" 1 (and (eq_attr "cpu" "r5500") (eq_attr "type" "arith,shift,slt,clz,const,nop,trap")) "vr55_dp0|vr55_dp1") -(define_insn_reservation "ir_vr55_imul_si" 3 +(define_bypass 2 + "ir_vr55_arith" + "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, + ir_vr55_idiv_si,ir_vr55_idiv_di") + +(define_insn_reservation "ir_vr55_mthilo" 1 + (and (eq_attr "cpu" "r5500") + (eq_attr "type" "mthilo")) + "vr55_mac") + +(define_insn_reservation "ir_vr55_mfhilo" 5 + (and (eq_attr "cpu" "r5500") + (eq_attr "type" "mfhilo")) + "vr55_mac") + +;; The default latency is for the GPR result of a mul. Bypasses handle the +;; latency of {mul,mult}->{mfhi,mflo}. +(define_insn_reservation "ir_vr55_imul_si" 5 (and (eq_attr "cpu" "r5500") (and (eq_attr "type" "imul") (eq_attr "mode" "SI"))) "vr55_mac") -(define_insn_reservation "ir_vr55_imul_di" 4 +;; The default latency is for pre-reload scheduling and handles the case +;; where a pseudo destination will be stored in a GPR (as it usually is). +;; The delay includes the latency of the dmult itself and the anticipated +;; mflo or mfhi. +;; +;; Once the mflo or mfhi has been created, bypasses handle the latency +;; between it and the dmult. +(define_insn_reservation "ir_vr55_imul_di" 9 (and (eq_attr "cpu" "r5500") (and (eq_attr "type" "imul") (eq_attr "mode" "DI"))) - "vr55_mac") + "vr55_mac*4") -(define_insn_reservation "ir_vr55_imadd_si" 3 +;; The default latency is as for ir_vr55_imul_si. +(define_insn_reservation "ir_vr55_imadd" 5 (and (eq_attr "cpu" "r5500") - (eq_attr "type" "imul")) + (eq_attr "type" "imadd")) "vr55_mac") +(define_bypass 1 + "ir_vr55_imul_si,ir_vr55_imadd" + "ir_vr55_imadd" + "mips_linked_madd_p") + +(define_bypass 2 + "ir_vr55_imul_si,ir_vr55_imadd" + "ir_vr55_mfhilo") + +(define_bypass 4 + "ir_vr55_imul_di" + "ir_vr55_mfhilo") + ;; Divide algorithm is early out with best latency of 7 pcycles. ;; Use worst case for scheduling purposes. (define_insn_reservation "ir_vr55_idiv_si" 42 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index d26626c99a5..ad5a48e8a40 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -2347,9 +2347,9 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total) *total = COSTS_N_INSNS (12); else if (TUNE_MIPS3900) *total = COSTS_N_INSNS (2); - else if (TUNE_MIPS5400 || TUNE_MIPS5500 || TUNE_SB1) - *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3); - else if (TUNE_MIPS7000) + else if (TUNE_MIPS5400 || TUNE_SB1) + *total = COSTS_N_INSNS (mode == DImode ? 4 : 3); + else if (TUNE_MIPS5500 || TUNE_MIPS7000) *total = COSTS_N_INSNS (mode == DImode ? 9 : 5); else if (TUNE_MIPS9000) *total = COSTS_N_INSNS (mode == DImode ? 8 : 3); -- 2.30.2