From 6164f23a9140ae8dfa4d44f7a9c41228e36fa9bf Mon Sep 17 00:00:00 2001 From: XiaoYuan Zheng Date: Thu, 22 Jan 2015 05:08:05 -0500 Subject: [PATCH] amdgpu/addrlib: add tcCompatible htile addr from coordinate support. --- src/amd/addrlib/addrinterface.h | 3 ++ src/amd/addrlib/core/addrlib1.cpp | 31 ++++++++++++-------- src/amd/addrlib/core/addrlib1.h | 8 +++++ src/amd/addrlib/r800/ciaddrlib.cpp | 47 +++++++++++++++++++++++++++++- src/amd/addrlib/r800/ciaddrlib.h | 4 +++ 5 files changed, 80 insertions(+), 13 deletions(-) diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index 01d8788f4b8..079596767e2 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -851,6 +851,7 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT UINT_32 slice; ///< Index of slice UINT_32 numSlices; ///< Number of slices BOOL_32 isLinear; ///< Linear or tiled HTILE layout + ADDR_HTILE_FLAGS flags; ///< htile flags AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 ADDR_TILEINFO* pTileInfo; ///< Tile info @@ -859,6 +860,8 @@ typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT /// while the global useTileIndex is set to 1 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) ///< README: When tileIndex is not -1, this must be valid + UINT_32 bpp; ///< depth/stencil buffer bit per pixel size + UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; /** diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index 1dc61e01273..f0fd08c3eb9 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -1422,18 +1422,25 @@ ADDR_E_RETURNCODE AddrLib1::ComputeHtileAddrFromCoord( if (returnCode == ADDR_OK) { - pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch, - pIn->height, - pIn->x, - pIn->y, - pIn->slice, - pIn->numSlices, - 1, - pIn->isLinear, - isWidth8, - isHeight8, - pIn->pTileInfo, - &pOut->bitPosition); + if (pIn->flags.tcCompatible) + { + HwlComputeHtileAddrFromCoord(pIn, pOut); + } + else + { + pOut->addr = HwlComputeXmaskAddrFromCoord(pIn->pitch, + pIn->height, + pIn->x, + pIn->y, + pIn->slice, + pIn->numSlices, + 1, + pIn->isLinear, + isWidth8, + isHeight8, + pIn->pTileInfo, + &pOut->bitPosition); + } } } diff --git a/src/amd/addrlib/core/addrlib1.h b/src/amd/addrlib/core/addrlib1.h index 1bdfd5bf8f2..25af637dcd0 100644 --- a/src/amd/addrlib/core/addrlib1.h +++ b/src/amd/addrlib/core/addrlib1.h @@ -290,6 +290,14 @@ protected: return ADDR_NOTSUPPORTED; } + /// Virtual function to get htile address for tc compatible htile + virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const + { + return ADDR_NOTSUPPORTED; + } + // Compute attributes // HTILE diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index d4f8c641b37..57416dced16 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -308,7 +308,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord( UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(fmaskAddress, 0, 0, - 4, + 4, // cmask 4 bits elemBits, blockByte, m_pipeInterleaveBytes, @@ -322,6 +322,51 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeCmaskAddrFromCoord( return returnCode; } + +/** +*************************************************************************************************** +* CiAddrLib::HwlComputeHtileAddrFromCoord +* +* @brief +* Compute tc compatible Htile address from depth/stencil address +* +* @return +* ADDR_E_RETURNCODE +*************************************************************************************************** +*/ +ADDR_E_RETURNCODE CiAddrLib::HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, ///< [in] depth/stencil addr/bpp/tile input + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] htile address + ) const +{ + ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED; + + if ((m_settings.isVolcanicIslands == TRUE) && + (pIn->flags.tcCompatible == TRUE)) + { + UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); + UINT_32 numOfBanks = pIn->pTileInfo->banks; + UINT_64 zStencilAddr = pIn->zStencilAddr; + UINT_32 elemBits = pIn->bpp; + UINT_32 blockByte = 64 * elemBits / 8; + UINT_64 metaNibbleAddress = HwlComputeMetadataNibbleAddress(zStencilAddr, + 0, + 0, + 32, // htile 32 bits + elemBits, + blockByte, + m_pipeInterleaveBytes, + numOfPipes, + numOfBanks, + 1); + pOut->addr = (metaNibbleAddress >> 1); + pOut->bitPosition = 0; + returnCode = ADDR_OK; + } + + return returnCode; +} + /** *************************************************************************************************** * CiAddrLib::HwlConvertChipFamily diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h index 1e3dc567125..750b2b382e1 100644 --- a/src/amd/addrlib/r800/ciaddrlib.h +++ b/src/amd/addrlib/r800/ciaddrlib.h @@ -154,6 +154,10 @@ protected: const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const; + virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( + const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const; + virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const; virtual VOID HwlPadDimensions( -- 2.30.2