From 617c6ecb478260a4a9d950363b70492b9adeb8af Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 30 Sep 2015 19:43:14 +0800
Subject: [PATCH] interconnect/stream: add multiplexer and demultiplexer

---
 misoc/interconnect/stream.py | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/misoc/interconnect/stream.py b/misoc/interconnect/stream.py
index 3e6cf619..bdbe53a4 100644
--- a/misoc/interconnect/stream.py
+++ b/misoc/interconnect/stream.py
@@ -113,3 +113,32 @@ class SyncFIFO(_FIFOWrapper):
 class AsyncFIFO(_FIFOWrapper):
     def __init__(self, layout, depth):
         _FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
+
+
+class Multiplexer(Module):
+    def __init__(self, layout, n):
+        self.source = Source(layout)
+        sinks = []
+        for i in range(n):
+            sink = Sink(layout)
+            setattr(self, "sink"+str(i), sink)
+            sinks.append(sink)
+        self.sel = Signal(max=n)
+
+        # # #
+
+        cases = {}
+        for i, sink in enumerate(sinks):
+            cases[i] = Record.connect(sink, self.source)
+        self.comb += Case(self.sel, cases)
+
+
+class Demultiplexer(Module):
+    def __init__(self, layout, n):
+        self.sink = Sink(layout)
+        sources = []
+        for i in range(n):
+            source = Source(layout)
+            setattr(self, "source"+str(i), source)
+            sources.append(source)
+        self.sel = Signal(max=n)
-- 
2.30.2