From 617e0e1d1225259b70d0fd9b50783a1e30758934 Mon Sep 17 00:00:00 2001 From: Daniel Berlin Date: Sun, 9 Dec 2001 18:49:30 +0000 Subject: [PATCH] rs6000.h (enum rs6000_builtins): Add remaining altivec builtins (VCF?X, VCT?XS, VSEL, V*EFP, VRFI*). 2001-12-09 Daniel Berlin * config/rs6000/rs6000.h (enum rs6000_builtins): Add remaining altivec builtins (VCF?X, VCT?XS, VSEL, V*EFP, VRFI*). * config/rs6000/rs6000.c: Ditto. * config/rs6000/rs6000.md: Ditto. From-SVN: r47814 --- gcc/ChangeLog | 9 +++ gcc/config/rs6000/rs6000.c | 71 +++++++++++++++++--- gcc/config/rs6000/rs6000.h | 16 +++++ gcc/config/rs6000/rs6000.md | 129 ++++++++++++++++++++++++++++++++++-- 4 files changed, 212 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 311c27137f5..a94566044f3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2001-12-09 Daniel Berlin + + * config/rs6000/rs6000.h (enum rs6000_builtins): Add remaining + altivec builtins (VCF?X, VCT?XS, VSEL, V*EFP, VRFI*). + + * config/rs6000/rs6000.c: Ditto. + + * config/rs6000/rs6000.md: Ditto. + 2001-12-09 Kaveh R. Ghazi * 1750a.md: Add default case in switch. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0cabac305cc..0203ff45580 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3021,11 +3021,15 @@ static const struct builtin_description bdesc_3arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, - { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, + { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, + { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, + { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, + { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, }; /* Simple binary operations: VECc = foo (VECa, VECb). */ @@ -3050,6 +3054,8 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, + { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, @@ -3063,6 +3069,8 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, + { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, @@ -3141,9 +3149,18 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, }; -/* Simple unary operations: VECb = foo (unsigned literal). */ +/* Simple unary operations: VECb = foo (unsigned literal) or VECb = + foo (VECa). */ static const struct builtin_description bdesc_1arg[] = { + { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, + { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, + { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, + { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, + { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, + { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, @@ -3524,6 +3541,10 @@ altivec_init_builtins (void) tree v16qi_ftype_char = build_function_type (V16QI_type_node, tree_cons (NULL_TREE, char_type_node, endlink)); + /* V4SF foo (V4SF) */ + tree v4sf_ftype_v4sf + = build_function_type (V4SF_type_node, + tree_cons (NULL_TREE, V4SF_type_node, endlink)); /* V4SI foo (int *). */ tree v4si_ftype_pint @@ -3573,6 +3594,16 @@ altivec_init_builtins (void) tree_cons (NULL_TREE, V4SI_type_node, endlink))); /* These are really for the unsigned 5 bit literals */ + tree v4sf_ftype_v4si_char + = build_function_type (V4SF_type_node, + tree_cons (NULL_TREE, V4SI_type_node, + tree_cons (NULL_TREE, char_type_node, + endlink))); + tree v4si_ftype_v4sf_char + = build_function_type (V4SI_type_node, + tree_cons (NULL_TREE, V4SF_type_node, + tree_cons (NULL_TREE, char_type_node, + endlink))); tree v4si_ftype_v4si_char = build_function_type (V4SI_type_node, tree_cons (NULL_TREE, V4SI_type_node, @@ -3594,7 +3625,13 @@ altivec_init_builtins (void) tree_cons (NULL_TREE, V4SF_type_node, tree_cons (NULL_TREE, V4SF_type_node, endlink))); - + tree v4sf_ftype_v4sf_v4sf_v4si + = build_function_type (V4SF_type_node, + tree_cons (NULL_TREE, V4SF_type_node, + tree_cons (NULL_TREE, V4SF_type_node, + tree_cons (NULL_TREE, + V4SI_type_node, + endlink)))); tree v4sf_ftype_v4sf_v4sf_v4sf = build_function_type (V4SF_type_node, tree_cons (NULL_TREE, V4SF_type_node, @@ -3602,6 +3639,13 @@ altivec_init_builtins (void) tree_cons (NULL_TREE, V4SF_type_node, endlink)))); + tree v4si_ftype_v4si_v4si_v4si + = build_function_type (V4SI_type_node, + tree_cons (NULL_TREE, V4SI_type_node, + tree_cons (NULL_TREE, V4SI_type_node, + tree_cons (NULL_TREE, + V4SI_type_node, + endlink)))); tree v8hi_ftype_v8hi_v8hi = build_function_type (V8HI_type_node, @@ -3732,6 +3776,9 @@ altivec_init_builtins (void) { switch (mode0) { + case V4SImode: + type = v4si_ftype_v4si_v4si_v4si; + break; case V4SFmode: type = v4sf_ftype_v4sf_v4sf_v4sf; break; @@ -3767,15 +3814,13 @@ altivec_init_builtins (void) } else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode && mode3 == V4SImode) - { type = v4si_ftype_v16qi_v16qi_v4si; - } else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode && mode3 == V4SImode) - { type = v4si_ftype_v8hi_v8hi_v4si; - } - + else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode + && mode3 == V4SImode) + type = v4sf_ftype_v4sf_v4sf_v4si; else abort (); @@ -3860,6 +3905,14 @@ altivec_init_builtins (void) else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) type = v16qi_ftype_v16qi_char; + /* vfloat, vint, 5 bit literal. */ + else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) + type = v4sf_ftype_v4si_char; + + /* vint, vfloat, 5 bit literal. */ + else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) + type = v4si_ftype_v4sf_char; + /* fixme: aldyh */ /* int, x, x. */ else if (mode0 == SImode) @@ -3907,6 +3960,8 @@ altivec_init_builtins (void) type = v8hi_ftype_char; else if (mode0 == V16QImode && mode1 == QImode) type = v16qi_ftype_char; + else if (mode0 == V4SFmode && mode1 == V4SFmode) + type = v4sf_ftype_v4sf; else abort (); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 9ad978e1d0f..14f38a166c8 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2909,6 +2909,10 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW, ALTIVEC_BUILTIN_VAVGSW, + ALTIVEC_BUILTIN_VCFUX, + ALTIVEC_BUILTIN_VCFSX, + ALTIVEC_BUILTIN_VCTSXS, + ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH, @@ -2922,6 +2926,8 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP, + ALTIVEC_BUILTIN_VEXPTEFP, + ALTIVEC_BUILTIN_VLOGEFP, ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, @@ -2963,6 +2969,10 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR, + ALTIVEC_BUILTIN_VSEL_4SI, + ALTIVEC_BUILTIN_VSEL_4SF, + ALTIVEC_BUILTIN_VSEL_8HI, + ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI, @@ -2978,9 +2988,15 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS, + ALTIVEC_BUILTIN_VREFP, + ALTIVEC_BUILTIN_VRFIM, + ALTIVEC_BUILTIN_VRFIN, + ALTIVEC_BUILTIN_VRFIP, + ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW, + ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b0c89191213..af9422bbbf8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -15046,11 +15046,11 @@ [(set_attr "type" "vecsimple")]) (define_insn "ftruncv4sf2" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vrfiz %0, %1" - [(set_attr "type" "vecfloat")]) + [(set (match_operand:V4SF 0 "register_operand" "=v") + (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vrfiz %0, %1" + [(set_attr "type" "vecfloat")]) (define_insn "altivec_vperm_4si" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -15087,3 +15087,122 @@ "TARGET_ALTIVEC" "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vrfip" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] + "TARGET_ALTIVEC" + "vrfip %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrfin" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] + "TARGET_ALTIVEC" + "vrfin %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrfim" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] + "TARGET_ALTIVEC" + "vrfim %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vcfux" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 151))] + "TARGET_ALTIVEC" + "vcfux %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vcfsx" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 152))] + "TARGET_ALTIVEC" + "vcfsx %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vctuxs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 153))] + "TARGET_ALTIVEC" + "vctusx %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vctsxs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 154))] + "TARGET_ALTIVEC" + "vctsxs %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vlogefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] + "TARGET_ALTIVEC" + "vlogefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vexptefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] + "TARGET_ALTIVEC" + "vexptefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrsqrtefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] + "TARGET_ALTIVEC" + "vrsqrtefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] + "TARGET_ALTIVEC" + "vrefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vsel_4si" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 159))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 160))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V8HI 3 "register_operand" "v")] 161))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 162))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + + -- 2.30.2