From 618eef38d9d18342930fbc960e5b9c23e6185b40 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Tue, 2 Apr 2019 10:56:34 +0000 Subject: [PATCH] S/390: arch13: Add support for new select instruction Compared to the load on condition instructions we already have the new select instruction allows to have a THEN and and ELSE source operand - but only for register to register loads. gcc/ChangeLog: 2019-04-02 Andreas Krebbel * config/s390/s390.c (s390_rtx_costs): Do not add extra costs for if-then-else constructs if we can use the select instruction. * config/s390/s390.md ("*movcc"): Add the new instructions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel * gcc.target/s390/arch13/sel-1.c: New test. From-SVN: r270080 --- gcc/ChangeLog | 6 ++++++ gcc/config/s390/s390.c | 3 ++- gcc/config/s390/s390.md | 17 ++++++++-------- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/s390/arch13/sel-1.c | 21 ++++++++++++++++++++ 5 files changed, 42 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/s390/arch13/sel-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6601061c39a..bc1653e1009 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-04-02 Andreas Krebbel + + * config/s390/s390.c (s390_rtx_costs): Do not add extra costs for + if-then-else constructs if we can use the select instruction. + * config/s390/s390.md ("*movcc"): Add the new instructions. + 2019-04-02 Andreas Krebbel * config/s390/s390.md ("*popcountdi_arch13_cc") diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 7cf1d67e985..bceaca3fbc8 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -3529,7 +3529,8 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code, /* It is a real IF-THEN-ELSE. An additional move will be needed to implement that. */ - if (reload_completed + if (!TARGET_ARCH13 + && reload_completed && !rtx_equal_p (dst, then) && !rtx_equal_p (dst, els)) *total += COSTS_N_INSNS (1) / 2; diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 018020cd19d..514bd2414c4 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -6701,27 +6701,28 @@ -; locr, loc, stoc, locgr, locg, stocg, lochi, locghi +; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr (define_insn "*movcc" - [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") + [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") (if_then_else:GPR (match_operator 1 "s390_comparison" - [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") - (match_operand 5 "const_int_operand" "")]) - (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") - (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] + [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") + (match_operand 5 "const_int_operand" "")]) + (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0") + (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] "TARGET_Z196" "@ locr%C1\t%0,%3 locr%D1\t%0,%4 + selr%C1\t%0,%3,%4 loc%C1\t%0,%3 loc%D1\t%0,%4 lochi%C1\t%0,%h3 lochi%D1\t%0,%h4 stoc%C1\t%3,%0 stoc%D1\t%4,%0" - [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") - (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) + [(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") + (set_attr "cpu_facility" "*,*,arch13,*,*,z13,z13,*,*")]) ;; ;;- Multiply instructions. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8bc2b862b09..087e82bdce9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-04-02 Andreas Krebbel + + * gcc.target/s390/arch13/sel-1.c: New test. + 2019-04-02 Andreas Krebbel * gcc.target/s390/arch13/popcount-1.c: New test. diff --git a/gcc/testsuite/gcc.target/s390/arch13/sel-1.c b/gcc/testsuite/gcc.target/s390/arch13/sel-1.c new file mode 100644 index 00000000000..301a133ea91 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/arch13/sel-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ + +int +sel32 (int a, int then, int els) +{ + return a > 42 ? then : els; +} + +/* FIXME: This currently fails since ifcvt considers that combination + too expensive. THe reason is that additional load instructions + emitted by ifcvt are part of the costs although these should get + removed later. */ +/* { dg-final { scan-assembler-times "\tselrh\t" 1 } } */ + +long long +sel64 (int a, long long then, long long els) +{ + return a > 42 ? then : els; +} + +/* { dg-final { scan-assembler-times "\tselgrh\t" 1 } } */ -- 2.30.2