From 61b8958953eb062e08a1c6994b255c1f79c57dd8 Mon Sep 17 00:00:00 2001 From: Nina Engelhardt Date: Fri, 26 Jul 2013 15:48:25 +0200 Subject: [PATCH] fix synthesis translate on/off switch --- migen/fhdl/verilog.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index f608338c..67402754 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -169,8 +169,8 @@ def _printcomb(f, ns, display_run): if f.comb: # Generate a dummy event to get the simulator # to run the combinatorial process once at the beginning. - syn_off = "// synthesis translate off\n" - syn_on = "// synthesis translate on\n" + syn_off = "// synthesis translate_off\n" + syn_on = "// synthesis translate_on\n" dummy_s = Signal(name_override="dummy_s") r += syn_off r += "reg " + _printsig(ns, dummy_s) + ";\n" -- 2.30.2